Multi-gate transistors and methods of forming the same

A method, comprising:

• depositing a buffer layer over a substrate having a buried oxide layer;
• forming a stack on the buffer layer, wherein the stack comprises:
• a plurality of channel layers,
• a plurality of sacrificial layers interleaving the plurality of channel layers, and
• a plurality of cap layers disposed between interfaces between the plurality of channel layers and the plurality of sacrificial layers;
• forming a fin-shaped structure from the stack, the buffer layer and the substrate, the fin-shaped structure comprising a channel region and a source/drain region,
• forming an isolation feature to interface a lower portion of the fin-shaped structure;
• forming a dummy gate stack over the channel region of the fin-shaped structure;
• depositing a gate spacer layer over the dummy gate stack;
• recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of channel layers and the plurality of sacrificial layers;
• selectively and partially recessing the plurality of sacrificial layers to form a plurality of inner spacer recesses;
• forming a plurality of inner spacer features in the plurality of inner spacer recesses;
• forming a source/drain feature in the source/drain trench;
• removing the dummy gate stack;
• selectively removing the plurality of sacrificial layers to release the plurality of channel layers in the channel region as a plurality of channel members;
• and
• forming a gate structure around each of the plurality of channel members,
• wherein each of the plurality of cap layers comprises:
• a first cap layer interfacing the plurality of channel layers, and
• a second cap layer interfacing the plurality of sacrificial layers,
• wherein the selectively and partially recessing comprises selectively and partially recessing the second cap layers,
• wherein the plurality of inner spacer features are spaced apart from the plurality of channel layers by the first cap layers.

A method, comprising:

• depositing a buffer layer over a substrate;
• forming a stack on the buffer layer, wherein the stack comprises:
• a plurality of channel layers,
• a plurality of sacrificial layers interleaving the plurality of channel layers, and
• at least one cap layer disposed between each of the plurality of channel layers and an adjacent one of the plurality of sacrificial layers;
• forming a fin-shaped structure from the stack, the buffer layer and the substrate, the fin-shaped structure comprising a channel region and a source/drain region,
• forming a dummy gate stack over the channel region of the fin-shaped structure;
• depositing a gate spacer layer over the dummy gate stack;
• recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of channel layers and the plurality of sacrificial layers;
• selectively and partially recessing the plurality of sacrificial layers and a portion of the at least one cap layer to form a plurality of inner spacer recesses;
• forming a plurality of inner spacer features in the plurality of inner spacer recesses;
• forming a source/drain feature in the source/drain trench;
• removing the dummy gate stack;
• selectively removing the plurality of sacrificial layers to release the plurality of channel layers in the channel region as a plurality of channel members;
• and
• forming a gate structure around each of the plurality of channel members,
• wherein a composition of the at least one cap layer is different from a composition of the plurality of channel layers or a composition of the plurality of sacrificial layers.