One-time-programmable memory array having different device characteristics and methods of manufacturing thereof

A memory device, comprising:

• a plurality of memory cells, each memory cell comprising a first transistor of a plurality of first transistors;
• a driver circuit adjacent to the plurality of memory cells, the driver circuit comprising a plurality of second transistors each corresponding to one of the plurality of first transistors;
• a plurality of metal structures, each metal structure operatively coupling a respective memory cell and a respective second transistor of the driver circuit;
• and
• a plurality of metallization layers disposed between the plurality of metal structures and both of the plurality of first transistors and the plurality of second transistors;
• wherein at least one first transistor activates a corresponding second transistor in response to the at least one first transistor receiving, via at least one corresponding word line of the at least one first transistor, a corresponding threshold voltage;
• and
• wherein the at least one corresponding second transistor is configured to apply a reading voltage or a programming voltage to the at least one corresponding memory cell in response to activation of the at least one first transistor.

A memory device, comprising:

• a memory array comprising a plurality of memory cells, each memory cell comprising an access transistor of a plurality of access transistors;
• a driver circuit adjacent to the plurality of memory cells, the driver circuit comprising a plurality of peripheral transistors each corresponding to one of the plurality of access transistors;
• a plurality of bit lines, each bit lines operatively coupling a respective memory cell and a respective peripheral transistor of the driver circuit;
• and
• a plurality of metallization layers disposed between the plurality of bit lines and both of the plurality of access transistors and the plurality of peripheral transistors;
• wherein at least one access transistor activates at least one corresponding peripheral transistor in response to the at least one access transistor receiving, via at least one corresponding word line of the at least one access transistor, at corresponding threshold voltage;
• and
• wherein the at least one corresponding peripheral transistor is configured to apply a reading voltage or a programming voltage to at least one corresponding memory cell in response to activation of the at least one access transistor.