Configurable logic system and method for pipelined data transfer
AssigneeEfinix, Inc.
InventorsKok Yoong FOO, Jia Chi KOE
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Abstract
The present invention relates to a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave; and the method of implementation, wherein said system (101) comprises of at least one first register (112) configured to store and transfer at least one data from said master to said slave; wherein said system (101) is configured to operate on one clock and one reset. The system (101) further comprises of at least one first control logic (118) that controls said first register (112) and fourth register (109) to provide hold to the ready signal from the slave to ease timing closure at high speed.
Claims6
A configurable logic system (101) programmed to model a logic design for data pipeline between master and slave comprising:
- at least one first register (112) configured to store and transfer at least one data from said master to said slave;
- wherein said configurable logic system (101) is configured to operate on one clock and one reset;
- characterized in that said first register (112) is connected to at least one first control logic (118);
- said first register (112) is configured to be enabled by said first control logic (118);
- said first register (112) is configured to hold transfer of all or selected data to said slave when the ready signal from said slave is de-asserted;
- said system (101) further comprises of at least one second control logic (107) receiving said ready signal from said slave;
- and connected to said first control logic (118) to enable at least one fourth register (109);
- said first control logic (118) connected to at least one first multiplexer (117);
- said first control logic (118) configured to select, by controlling said first multiplexer (117) whether at least one second register (103) receives data directly from said master, or data from said first register (112);
- said system further comprises of at least one third register (105) configured to receive valid signal from said master through said first control logic (118);
- said third register (105) is configured to be enabled by said first control logic (118);
- said third register (105) configured to send valid signal to said slave;
- said first control logic (118) is connected to at least one second multiplexer (119);
- said first control logic (118) is configured to select, by controlling said second multiplexer (119), whether the value of ready signal to said master is based on the ready signal from said slave or output of said fourth register (109);
- wherein said fourth register (109) is configured to register the ready signal from the slave to the master;
- said second control logic (107) connected to at least one third multiplexer (121);
- said second control logic (107) is configured to select, by controlling said third multiplexer (121), whether data to be sent to the slave is from said second register (103) or said first register (112).
A method of implementing a configurable logic system (101) programmed to model a logic design for data pipeline between master and slave, comprising the steps of:
- (i) holding transfer of all or selected data from said master to said slave by at least one first register (112) when the ready signal from said slave is de-asserted;
- wherein said first register (112) is configured to be enabled by said first control logic (118);
- (ii) asserting valid signal from said master to said slave by at least one third register (105);
- wherein said third register (105) is configured to receive said valid signal from said master through said first control logic (118);
- wherein said third register (105) is configured to be enabled by said first control logic (118);
- (iii) receiving asserted said ready signal from said slave by at least one second control logic (107);
- wherein said second control logic (107) is connected to said first control logic (118) to enable said first register (112);
- (iv) registering said ready signal from said slave to said master by at least one fourth register (109);
- wherein said first control logic (118) is configured to select, by controlling at least one second multiplexer (119), whether the value of ready signal to said master is based on the ready signal from said slave or output of said fourth register (109);
- (v) send data from said master to said slave;
- wherein said first control logic (118) configured to select, by controlling at least one first multiplexer (117) whether at least one second register (103) receives data directly from said master, or data from said first register (112);
- wherein said second control logic (107) is configured to select, by controlling at least one third multiplexer (121), whether data to be sent to the slave is from said second register (103) or said first register (112);
- wherein said configurable logic system (101) is configured to operate on one clock and one reset.
Dependencies are inferred from the claim text.