Isolation module for backside power delivery

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET), comprising:

• performing a placeholder forming process to form placeholders, each interfacing with an extension region electrically isolated from replacement-metal-gate (RMG) stacks by inner spacers, in recesses formed within portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into a front inter-layer dielectric (ILD) formed on the substrate;
• performing a placeholder removal process to remove the placeholders selectively to the substrate and the STIs;
• performing a substrate nitridation process to form nitride layers on inner surfaces of the recesses;
• performing a cavity shaping process to form a cavity at an exposed surface of the extension region within each of the recesses, and a contact formation process to form a contact layer within the cavity;
• performing a silicide formation process to form an interface on the contact layer, and a contact metallization process to form a metal contact within each of the recesses;
• performing a substrate removal process to selectively etch the substrate against the RMG stacks and form ILD recesses between adjacent metal contacts;
• performing a liner deposition process to form a dielectric liner surrounding the metal contacts;
• and
• performing an oxide fill process to form a back ILD in each of the ILD recesses.

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET), comprising:

• performing a placeholder removal process to remove placeholders formed in recesses within portions of a substrate isolated by shallow trench isolations (STIs), selectively to the substrate and the STIs, wherein:
• each of the placeholders interfaces with an extension region electrically isolated from replacement-metal-gate (RMG) stacks by inner spacers, and
• the recesses extending into a front inter-layer dielectric (ILD) formed on the substrate;
• performing a contact formation process to form a contact layer on an exposed surface of the extension region within each of the recesses;
• performing a silicide formation process to form an interface on the contact layer, and a contact metallization process to form a metal contact within each of the recesses;
• performing a substrate removal process to selectively etch the substrate against the RMG stacks and form ILD recesses between adjacent metal contacts;
• performing a liner deposition process to form a dielectric liner surrounding the metal contacts;
• and
• performing an oxide fill process to form a back ILD in each of the ILD recesses.