Self-aligned spacers for multi-gate devices and method of fabrication thereof

A semiconductor device, comprising:

• a plurality of channel members vertically stacked;
• first and second gate sidewall spacers disposed above a topmost one of the channel members;
• a metal gate feature disposed between the first and second gate sidewall spacers, the metal gate feature wrapping around at least one of the channel members;
• an epitaxial feature abutting the channel members;
• and
• a dielectric feature interposing the metal gate feature and the epitaxial feature,
• wherein in a side view of the semiconductor device, the dielectric feature has upper and lower portions interfacing with two adjacent ones of the channel members and a center portion vertically stacked between the upper and lower portions, and wherein in a lengthwise direction of the channel members the center portion of the dielectric feature is thinner than the upper and lower portions of the dielectric feature.

A method of fabricating a semiconductor device, comprising:

• forming a stack of first type and second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and the first type and second type epitaxial layers being alternatingly disposed in a vertical direction;
• patterning the stack to form a fin-shaped structure;
• forming a dummy gate covering a channel region of the fin-shaped structure;
• forming a gate sidewall spacer layer extending along sidewalls of the dummy gate;
• etching a source/drain region of the fin-shaped structure to form a source/drain trench;
• epitaxially growing a source/drain feature in the source/drain trench;
• removing the dummy gate to form a gate trench, wherein the gate trench exposes opposing sidewalls of the gate sidewall spacer layer;
• removing the second type epitaxial layers from the gate trench;
• forming a dielectric material containing layer in the gate trench and in gaps between two adjacent ones of the first type epitaxial layers, the dielectric material containing layer interfacing with the gate sidewall spacer layer and the source/drain feature, the forming of the dielectric material containing layer including a thermal treatment to increase an oxygen concentration in the dielectric material containing layer;
• and
• depositing a metal gate feature in the gate trench and wrapping around the first type epitaxial layers.