Gilbert mixer

A Gilbert mixer comprising:

• first and second multi-finger field effect transistor (FET) devices, each FET device comprising a plurality of gate fingers arranged along a longitudinal axis between alternating source terminals and drain terminals, wherein the plurality of gate fingers of each FET device extend transverse to the longitudinal axis of the FET devices;
• first and second pairs of voltage rails arranged parallel to the longitudinal axis across the first and second FET devices respectively, each of the first and second pairs of voltage rails comprising an upper rail and a lower rail;
• a first gate interconnect connecting the upper rail of the first pair of voltage rails and the lower rail of the second pair of voltage rails to a first input terminal;
• and
• a second gate interconnect connecting the lower rail of the first pair of voltage rails and the upper rail of the second pair of voltage rails to a second input terminal,
• wherein alternating adjacent pairs of gate fingers of the first FET device are connected to respective upper and lower rails of the first pair of voltage rails and alternating adjacent pairs of gate fingers of the second FET device are connected to respective upper and lower rails of the second pair of voltage rails.

A radar transmitter comprising a Gilbert mixer, the Gilbert mixer comprising:

• first and second multi-finger field effect transistor (FET) devices, each FET device comprising a plurality of gate fingers arranged along a longitudinal axis between alternating source terminals and drain terminals, wherein the plurality of gate fingers of each FET device extend transverse to the longitudinal axis of the FET devices;
• first and second pairs of voltage rails arranged parallel to the longitudinal axis across the first and second FET devices respectively, each of the first and second pairs of voltage rails comprising an upper rail and a lower rail;
• a first gate interconnect connecting the upper rail of the first pair of voltage rails and the lower rail of the second pair of voltage rails to a first input terminal;
• and
• a second gate interconnect connecting the lower rail of the first pair of voltage rails and the upper rail of the second pair of voltage rails to a second input terminal,
• wherein alternating adjacent pairs of gate fingers of the first FET device are connected to respective upper and lower rails of the first pair of voltage rails and alternating adjacent pairs of gate fingers of the second FET device are connected to respective upper and lower rails of the second pair of voltage rails.