Sequential self-aligning method in complementary field effect transistor devices

A method of forming a complementary field-effect transistor (CFET), comprising:

• forming a bottom device structure on a device substrate, wherein the device substrate comprises a first substrate layer, wherein the bottom device structure is disposed above the first substrate layer;
• the bottom device structure comprising:
• a sacrificial superlattice layer;
• a plurality of channel layers disposed over the sacrificial superlattice layer, wherein the plurality of channel layers extend through a dummy gate layer, and the plurality of channel layers are separated by a plurality of sacrificial layers;
• forming a top device structure, wherein the top device structure is disposed above the bottom device structure;
• the top device structure comprising:
• a sacrificial superlattice layer;
• a plurality of channel layers disposed over the sacrificial superlattice layer, wherein the plurality of channel layers extend through a dummy gate layer, and the plurality of channel layers are separated by a plurality of sacrificial layers;
• replacing the sacrificial superlattice layer of the bottom device structure with an isolation structure, and the sacrificial superlattice layer of the top device structure with an isolation structure;
• disposing a first dielectric fill layer over the bottom device structure;
• forming an N-channel metal-oxide semiconductor (NMOS) device from the top device structure, wherein forming the NMOS device comprises:
• removing the plurality of sacrificial layers from the top device structure;
• performing an epitaxial (epi) process to form an n-type source-drain region on at least one exposed surface of the plurality of channel layers of the top device structure;
• performing a replacement metal gate (RMG) process to replace the dummy gate layer of the top device structure with a metal gate;
• and
• disposing a second dielectric fill layer over the NMOS device;
• bonding a second substrate layer over the NMOS device;
• removing the first substrate layer;
• removing the first dielectric fill layer;
• forming a P-channel metal-oxide semiconductor (PMOS) device from the bottom device structure, wherein forming the PMOS device comprises:
• removing the plurality of sacrificial layers from the bottom device structure;
• performing an epitaxial process to form p-type source/drain region on region on at least one exposed surface of the plurality of channel layers of the bottom device structure;
• performing a RMG process to replace the dummy gate layer of the bottom device structure with a metal gate;
• and
• disposing a third dielectric fill layer over the PMOS device;
• forming backside device contacts over the PMOS device;
• bonding a third substrate layer over the backside device contacts;
• removing the second substrate layer;
• and
• forming frontside device contacts over the NMOS device.

A method of forming a complementary field-effect transistor (CFET), comprising:

• forming a bottom device structure on a device substrate, wherein the device substrate comprises a first substrate layer, wherein the bottom device structure is disposed above the first substrate layer;
• the bottom device structure comprising:
• a sacrificial superlattice layer;
• a plurality of channel layers disposed over the sacrificial superlattice layer, wherein the plurality of channel layers extend through a dummy gate layer, and the plurality of channel layers are separated by a plurality of sacrificial layers;
• forming a top device structure, wherein the top device structure is disposed above the bottom device structure;
• the top device structure comprising:
• a sacrificial superlattice layer;
• a plurality of channel layers disposed over the sacrificial superlattice layer, wherein the plurality of channel layers extend through a dummy gate layer, and the plurality of channel layers are separated by a plurality of sacrificial layers;
• replacing the sacrificial superlattice layer of the bottom device structure with an isolation structure, and the sacrificial superlattice layer of the top device structure with an isolation structure;
• disposing a first dielectric fill layer over the bottom device structure;
• forming an P-channel metal-oxide semiconductor (PMOS) device from the top device structure, wherein forming the PMOS device comprises:
• removing the plurality of sacrificial layers from the top device structure;
• performing an epitaxial (epi) process to form an p-type source-drain region on at least one exposed surface of the plurality of channel layers of the top device structure;
• performing a replacement metal gate (RMG) process to replace the dummy gate layer of the top device structure with a metal gate;
• and
• disposing a second dielectric fill layer over the PMOS device;
• bonding a second substrate layer over the PMOS device;
• removing the first substrate layer;
• removing the first dielectric fill layer;
• forming a N-channel metal-oxide semiconductor (NMOS) device from the bottom device structure, wherein forming the NMOS device comprises:
• removing the plurality of sacrificial layers from the bottom device structure;
• performing an epitaxial process to form n-type source/drain region on region on at least one exposed surface of the plurality of channel layers of the bottom device structure;
• performing a RMG process to replace the dummy gate layer of the bottom device structure with a metal gate;
• and
• disposing a third dielectric fill layer over the NMOS device;
• forming backside device contacts over the NMOS device;
• bonding a third substrate layer over the backside device contacts;
• removing the second substrate layer;
• and
• forming frontside device contacts over the PMOS device.