Semiconductor device including a multi-bridge channel field-effect transistor

A semiconductor device, comprising:

• a substrate;
• an active pattern on the substrate and extending in a first horizontal direction on the substrate;
• a first gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern;
• a second gate electrode extending in the second horizontal direction on the active pattern, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction;
• a gate insulating layer disposed on sidewalls of the first gate electrode in the first horizontal direction;
• a trench formed on the active pattern between the first gate electrode and the second gate electrode, the trench extending into the active pattern;
• a lower spacer disposed along a bottom surface of the trench, an uppermost surface of the lower spacer being formed at a first level that is lower than a second level of an uppermost surface of the active pattern;
• a source/drain region on the lower spacer within the trench;
• and
• a void formed within the trench between the lower spacer and the source/drain region, an uppermost surface of the void being formed at a third level that is higher than the second level of the uppermost surface of the active pattern,
• wherein the source/drain region comprises:
• a first layer in contact with sidewalls of the gate insulating layer in the first horizontal direction and the uppermost surface of the lower spacer;
• a second layer on the first layer, at least a portion of the second layer being exposed through the void;
• and
• a third layer on the second layer, at least a portion of the third layer being exposed through the void.

A semiconductor device, comprising:

• a substrate;
• an active pattern on the substrate and extending in a first horizontal direction;
• a first plurality of nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction;
• a second plurality of nanosheets stacked on the active pattern and spaced apart from one another in the vertical direction, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction;
• a first gate electrode on the active pattern and extending in a second horizontal direction different from the first horizontal direction, the first gate electrode at least partially surrounding the first plurality of nanosheets;
• a second gate electrode on the active pattern and extending in the second horizontal direction, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction, the second gate electrode at least partially surrounding the second plurality of nanosheets;
• a first gate insulating layer disposed on sidewalls of the first gate electrode in the first horizontal direction;
• a second gate insulating layer disposed on sidewalls of the second gate electrode in the first horizontal direction;
• a trench formed on the active pattern between the first plurality of nanosheets and the second plurality of nanosheets, the trench extending into the active pattern;
• a lower spacer disposed along a bottom surface of the trench, an uppermost surface of the lower spacer being formed at a first level that is lower than a second level of an uppermost surface of the active pattern;
• a source/drain region on the lower spacer within the trench;
• and
• a void formed within the trench between the lower spacer and the source/drain region, an uppermost surface of the void being formed at a third level that is higher than the second level of the uppermost surface of the active pattern, a lowermost surface of the void being formed at a fourth level that is lower than the first level of the uppermost surface of the lower spacer, an upper surface of the void being formed convexly toward the source/drain region,
• wherein the source/drain region comprises:
• a first layer in contact with sidewalls of each of the first gate insulating layer and the second gate insulating layer in the first horizontal direction and the uppermost surface of the lower spacer;
• a second layer on the first layer, at least a portion of the second layer being exposed through the void;
• and
• a third layer on the second layer, at least a portion of the third layer being exposed through the void.