US 2025/0328293 A1 · ENDURANCE GROUP FOR TIERED STORAGE APPLICATIONS

Abstract

Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.

Claims30

Dependent claims

A memory system, comprising:

one or more memory devices;
and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive an indication of a capacity identifier for a memory array in the memory system;
determine, based at least in part on the capacity identifier, an endurance group for a set of memory cells in the memory array, wherein the endurance group is associated with a set of trim parameters for data storage using the set of memory cells;
and
configuring, in accordance with the set of trim parameters for the endurance group, the set of memory cells and a namespace associate with the set of memory cells, wherein the namespace corresponds to a range of addresses that includes the set of memory cells in the memory array.

4 more elements

A memory system, comprising:

one or more memory dies, wherein each memory die of the one or more memory dies comprises:
a memory array comprising a plurality of memory cells;
a first set of memory cells from among the plurality of memory cells in the memory array, the first set of memory cells associated with a first endurance group, wherein the first endurance group is associated with a first set of trim parameters for data storage using the first set of memory cells;
a second set of memory cells from among the plurality of memory cells in the memory array, the second set of memory cells associated with a second endurance group, wherein the second endurance group is associated with a second set of trim parameters for data storage using the second set of memory cells;
and
one or more controllers coupled with the one or more memory dies and configured to:
configure the plurality of memory cells in the memory array to include the first set of memory cells associated with the first set of trim parameters and the second set of memory cells associated with the second set of trim parameters based at least in part on a capacity identifier that indicates the first endurance group and the second endurance group.

4 more elements

A memory system, comprising:

one or more memory devices;
and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
configure a plurality of memory cells of a memory device within the memory system to include a first set of memory cells associated with a first endurance group and a second set of memory cells associated with a second endurance group, wherein the first endurance group is associated with a first set of trim parameters for data storage and the second endurance group is associated with a second set of trim parameters for data storage;
receive, from a host device, signaling that indicates a movement of data from a first namespace within the memory device to a second namespace within the memory device, wherein the first namespace comprises a range of addresses associated with the first set of memory cells configured to store the data according to the first set of trim parameters associated with the first endurance group, and wherein the second namespace comprises a second range of addresses associated with the second set of memory cells configured to store the data according to the second set of trim parameters associated with the second endurance group;
and
transfer, within the memory device, the data from the first set of memory cells to the second set of memory cells based at least in part on the signaling.

4 more elements

A method by a memory system, comprising:

receiving an indication of a capacity identifier for a memory array in the memory system;
determining, based at least in part on the capacity identifier, an endurance group for a set of memory cells in the memory array, wherein the endurance group is associated with a set of trim parameters for data storage using the set of memory cells;
and
configuring, in accordance with the set of trim parameters for the endurance group, the set of memory cells and a namespace associated with the set of memory cells, wherein the namespace corresponds to a range of addresses that includes the set of memory cells in the memory array.

1 more element

Dependencies are inferred from the claim text.

Endurance group for tiered storage applications

Life of this patent

Endurance group for tiered storage applications

Life of this patent

Abstract

Claims30