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US 2025/0328291 A1Published application
Memory device
AssigneeKioxia Corporation
InventorsAkio SUGAHARA, Yuji NAGAI
Life of this patent
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Abstract
A memory system includes a memory device and a memory controller. The memory device includes first to fourth pads to which respective first to fourth signals are sent from the memory controller, a memory cell array configured to store data, and a data input and output interface. The data input and output interface is configured to receive the first signal input to the first pad as a command based on a timing of a first rising edge of the fourth signal at the fourth pad after a rising edge of the second signal at the second pad, and to receive the first signal input to the first pad as an address in response to a second rising edge of the fourth signal at the fourth pad after a rising edge of the third signal at the third pad.
Claims18
A memory system comprising:
- a memory device;
- and
- a memory controller,
- wherein the memory device comprises:
- a first pad to which a first signal sent from the memory controller is input;
- a second pad to which a second signal sent from the memory controller is input;
- a third pad to which a third signal sent from the memory controller is input;
- a fourth pad to which a fourth signal sent from the memory controller is input;
- a memory cell array configured to store data;
- a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, the data input and output interface being configured to (i) receive the first signal being input to the first pad as the command in response to a first rising edge of the fourth signal at the fourth pad after a rising edge of the second signal at the second pad, and (ii) receive the first signal being input to the first pad as the address in response to a second rising edge of the fourth signal at the fourth pad after a rising edge of the third signal at the third pad;
- a command register configured to store the command sent from the data input and output interface;
- and
- an address register configured to store the address sent from the data input and output interface,
- wherein a first period from the rising edge of the second signal to the first rising edge of the fourth signal is longer than a second period from the rising edge of the third signal to the second rising edge of the fourth signal, and
- wherein a third period from the first rising edge to the second rising edge of the third signal is shorter than the first period and longer than the second period.
12 more elements
A non-volatile semiconductor memory device comprising:
- a first pad configured to receive a first signal sent from an external memory controller;
- a second pad configured to receive a second signal sent from the external memory controller;
- a third pad configured to receive a third signal sent from the external memory controller;
- a fourth pad configured to receive a fourth signal sent from the external memory controller;
- a memory cell array configured to store data, the memory cell array including a memory cell block, and the memory cell block including a plurality of memory cell transistors arranged in a matrix;
- a sense amplifier configured to read the data from the memory cell transistor;
- a data register configured to store supplied data;
- a data input and output interface configured to receive a command, an address, and data to be written into at least one of the memory cell transistors from the external memory controller, and to output data read from the at least one of the memory cell transistors to the external memory controller, the data input and output interface being configured to (i) receive the first signal at the first pad as the command in response to a first rising edge of the fourth signal at the fourth pad, the first rising edge of the fourth signal being provided after elapse of a first period from a rising edge of the second signal at the second pad, and (ii) receive the first signal at the first pad as the address in response to a second rising edge of the fourth signal at the fourth pad, the second rising edge of the fourth signal being provided after elapse of a second period from a rising edge of the third signal at the third pad;
- a command register configured to store the command sent from the data input and output interface;
- and
- an address register configured to store the address sent from the data input and output interface,
- wherein a third period from the first rising edge to the second rising edge of the third signal is shorter than the first period and longer than the second period.
9 more elements
Dependencies are inferred from the claim text.