Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device

A method of manufacturing a memory device, the method comprising:

• preparing a peripheral circuit chip including a two-dimensional (2D) cell array including at least one information data block storing information data and a peripheral circuit connected to the 2D cell array;
• reading the information data based on performing an information data read (IDR) operation on the peripheral circuit chip;
• and
• fabricating the memory device based on bonding a memory chip including a three-dimensional (3D) cell array to the peripheral circuit chip, in response to a determination that the information data is valid information data.

A method of manufacturing a memory device, the method comprising:

• fabricating a peripheral circuit chip including a two-dimensional (2D) cell array and a peripheral circuit connected to the 2D cell array;
• performing an electrical die sorting (EDS) process on the peripheral circuit chip to inspect whether or not the 2D cell array and the peripheral circuit electrically operate;
• generating information data required for initializing settings of the memory device, based on a result of the EDS process, in response to a determination that the peripheral circuit chip has passed the EDS process;
• and
• programming the information data to the 2D cell array.

A method of manufacturing a memory device including a memory chip and a peripheral circuit chip, the method comprising:

• performing a first information data read (IDR) operation on a first block included in a test cell array of the peripheral circuit chip;
• performing a first dump-down operation on the first block;
• performing a second IDR operation on a second block included in the test cell array of the peripheral circuit chip, in response to a determination that the first IDR operation has failed;
• and
• performing a second dump-down operation on the second block,
• wherein the performing of the first dump-down operation includes sequentially storing information data read from the first block in a plurality of page buffers included in a page buffer circuit of the peripheral circuit chip.