System architecture and techniques for pinned memory migration
AssigneeIntel Corporation
InventorsUtkarsh Y. Kakaiya, Rajesh M. Sankaran, Sumedh S. Attarde, Philip R. Lantz, Andrew V. Anderson, Sanjay K. Kumar
Life of this patent
Estimating the term…
Abstract
Methods and apparatus relating to a system architecture and techniques for pinned memory migration are described. In an embodiment, one or more memory devices store a source page and a destination page. Logic circuitry causes a write operation from an Input/Output (I/O) device to be observed for both the source page and the destination page. A transactional memory copy operation is to be performed from the source page to the destination page. Other embodiments are also disclosed and claimed.
Claims20
An apparatus comprising:
- one or more memory devices to store a source page and a destination page;
- and
- logic circuitry to cause a write operation from an Input/Output (I/O) device to be observed for both the source page and the destination page,
- wherein a transactional memory copy operation is to be performed from the source page to the destination page.
One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
- store a source page and a destination page;
- cause, at Pinned Memory Migration (PMM) logic, a write operation from an Input/Output (I/O) device to be observed for both the source page and the destination page;
- and
- cause performance of a transactional memory copy operation from the source page to the destination page.
Dependencies are inferred from the claim text.