Memory cell array with increased source bias voltage

A method, comprising:

• providing a plurality of NOR flash memory cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of NOR flash memory cells consists of a dual-gate transistor, the dual-gate transistor comprising a silicon substrate, a channel layer over the silicon substrate, a first gate structure under the channel layer, and a second gate structure over the channel layer;
• providing a plurality of word lines extending in a first direction and electrically connected to the plurality of rows, respectively, and wherein the first gate structure and the second gate structure of the dual-gate transistor of each of the plurality of NOR flash memory cells are electrically connected to one of the plurality of word lines;
• electrically connecting a plurality of source lines extending in a second direction to the plurality of columns, respectively;
• and
• electrically connecting a plurality of bit lines extending in the second direction to the plurality of columns, respectively.

A method of fabricating a dual-gate transistor, comprising:

• providing a substrate;
• forming a first oxide layer on the substrate;
• forming a first gate structure embedded in the first oxide layer;
• forming a channel layer over the first gate structure;
• forming a second oxide layer on the channel layer;
• forming a trench in the second oxide layer to expose a portion of a top surface of the channel layer;
• and
• forming a second gate structure in the trench and over the channel layer.