Fast digital lane drop detection system for multi-lane direct detect transceivers

An optical transceiver, comprising:

• a plurality receivers each having a clock and data recovery (CDR) circuit;
• a plurality of optical drivers electrically coupled with the receivers via respective ones of a plurality of lanes;
• and
• a processor arranged to execute a program to perform operations, the operations comprising:
• capturing, from the CDR circuits, a phase interpolator (PI) control word for each lane of a plurality of lanes, wherein one lane of the plurality of lanes is assigned as a master lane and other ones of the plurality of lanes that are not the master lane are designated as non-master lanes;
• determining a lane difference between the master lane and each of the non-master lanes, with the lane difference being determined between the master lane and a given one of the non-master lanes as a difference between the PI control word associated with the master lane and the PI control word associated with the given one of the non-master lanes;
• calculating a difference associated with each one of the non-master lanes by determining a difference between the lane difference associated with a given one of the non-master lanes and a reference lane difference associated with the given one of the non-master lanes;
• upon determining that at least one of the differences has reached a drift threshold, determining that the master lane or one or more of the non-master lanes is invalid based on which of the differences have reached the drift threshold;
• and
• performing a control action when the master lane or one or more of the non-master lanes is invalid.

An optical module, comprising:

• an application-specific integrated circuit (ASIC);
• an optical transceiver electrically coupled with the ASIC by a plurality of lanes, and wherein the optical transceiver has a transmitter phase-locked loop (PLL) arranged to receive a phase interpolator (PI) control word from a master lane of the plurality of lanes;
• and
• a processor arranged to execute a program to perform operations, the operations comprising:
• capturing a PI control word for each lane of the plurality of lanes, wherein one lane of the plurality of lanes is assigned as the master lane and other ones of the plurality of lanes that are not the master lane are designated as non-master lanes;
• determining a lane difference between the master lane and each of the non-master lanes, with the lane difference being determined between the master lane and a given one of the non-master lanes as a difference between the PI control word associated with the master lane and the PI control word associated with the given one of the non-master lanes;
• calculating a difference associated with each one of the non-master lanes by determining a difference between the lane difference associated with a given one of the non-master lanes and a reference lane difference associated with the given one of the non-master lanes;
• upon determining that each one the differences has reached a drift threshold, determining that the master lane is invalid;
• and
• switching the master lane from the one lane to another lane of the plurality of lanes so that the transmitter PLL receives the PI control word from the other lane that is now the master lane.