Clock forwarded matched receiver with decision feedback equalizer

An integrated circuit comprising:

• a first summation circuit configured to:
• receive an analog signal;
• and
• apply a positive offset to the analog signal to generate a first internal signal;
• a second summation circuit configured to:
• receive the analog signal;
• and
• apply a negative offset to the analog signal to generate a second internal signal;
• a multiplexer configured to:
• receive a selection signal, wherein the selection signal is a feedback of a previous digital signal outputted by the multiplexer;
• select one of the first internal signal and the second internal signal;
• and
• output the selected one of the first internal signal and the second internal signal as a third internal signal;
• and
• a slicer configured to sample the third internal signal to generate a digital signal that represents a decoded bit value of the analog signal.

A system comprising:

• a controller configured to generate a strobe signal;
• a transmitter configured to output an analog signal;
• and
• a receiver configured to:
• receive the analog signal from the transmitter through a channel;
• apply a positive offset to the analog signal to generate a first internal signal;
• apply a negative offset to the analog signal to generate a second internal signal;
• sample at least one of the first internal signal and the second internal signal according to the strobe signal;
• use a previous digital signal as a selection signal to select a specific signal that decodes the analog signal;
• and
• based on the sample and the selection, generate a digital signal that represents a decoded bit value of the analog signal.