Vertical jfet semiconductor devices with avalanche current ballast resistance
AssigneeWolfspeed, Inc.
InventorRahul R. Potera
Life of this patent
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Abstract
A semiconductor device includes a semiconductor layer structure that includes an active region including a plurality of gate trenches, a plurality of gate contacts in respective ones of the gate trenches, a gate pad on the semiconductor layer structure, a gate bus extending from the gate pad, and a conductive path between the gate bus and a first one of the plurality of gate contacts. The conductive path includes a first resistivity region and at least one second resistivity region that has a higher resistivity than the first resistivity region.
Claims25
A semiconductor device, comprising:
- a semiconductor layer structure that comprises an active region including a plurality of gate trenches;
- a plurality of gate contacts in respective ones of the gate trenches;
- a gate pad on the semiconductor layer structure;
- a gate bus extending from the gate pad;
- and
- a conductive path between the gate bus and a first one of the plurality of gate contacts;
- wherein the conductive path includes a first resistivity region and at least one second resistivity region that has a higher resistivity than the first resistivity region.
A junction field effect transistor, comprising:
- a semiconductor layer structure;
- a gate pad on the semiconductor layer structure;
- a gate bus on the semiconductor layer structure, the gate bus electrically connected to the gate pad;
- and
- a plurality of gate contacts on and/or within the semiconductor layer structure that are electrically connected to the gate bus through a conductive interconnection region, the conductive interconnection region including a plurality of first resistivity regions and a plurality of second resistivity region that have a sheet resistance at least ten times greater than a sheet resistance of the first regions.
A semiconductor device, comprising:
- a semiconductor layer structure that comprises an active region including a plurality of gate trenches;
- a plurality of gate contacts in respective ones of the gate trenches;
- a gate pad on the semiconductor layer structure;
- a gate bus extending from the gate pad;
- and
- a conductive interconnection region in an electrical path between the gate bus and the plurality of gate contacts, wherein the conductive interconnection region includes a plurality of current steering structures that define a plurality of channels therebetween.
Dependencies are inferred from the claim text.