Flux agent and semiconductor package including cured product thereof

A semiconductor package comprising:

• a semiconductor substrate comprising an upper surface and a lower surface which are opposite to each other;
• a semiconductor chip including a first surface and a second surface which are opposite to each other, and disposed on the upper surface of the semiconductor substrate, wherein the first surface faces the upper surface of the semiconductor substrate;
• and
• a plurality of protective patterns interposed between the semiconductor substrate and the semiconductor chip, wherein each of the plurality of protective patterns is a cured product of a flux agent,
• wherein the flux agent comprises:
• a first compound comprising an ester group and an epoxy group;
• a fourth compound which is a chemical reactant of a second compound comprising an epoxy group and a third compound comprising an amine group and a carboxyl group;
• and
• a photoinitiator,
• wherein:
• the content of the first compound is 60 wt % to 95 wt % based on 100 wt % of the flux agent;
• the content of the fourth compound is 3 wt % to 33 wt % based on 100 wt % of the flux agent;
• and
• the content of the photoinitiator is 2 wt % to 10 wt % based on 100 wt % of the flux agent.

A semiconductor package comprising:

• a semiconductor substrate including an upper surface and a lower surface which are opposite to each other;
• a plurality of first conductive pads on the upper surface of the semiconductor substrate;
• a semiconductor chip comprising a first surface and a second surface which are opposite to each other, and disposed on the upper surface of the semiconductor substrate, wherein the first surface faces the upper surface of the semiconductor substrate;
• a plurality of second conductive pads on the first surface of the semiconductor chip;
• a plurality of connecting bumps interposed between the plurality of first conductive pads and the plurality of second conductive pads;
• and
• a plurality of protective patterns covering the plurality of connecting bumps, wherein a width in a first direction of each of the plurality of protective patterns decreases in a third direction farther from the upper surface of the semiconductor substrate, wherein the first direction is a direction parallel to the upper surface of the semiconductor substrate, wherein the third direction is a direction perpendicular to the upper surface of the semiconductor substrate.