Vertical semiconductor device and method for fabricating the vertical semiconductor device

A vertical semiconductor device, comprising:

• a lower stack including a source channel contact, wherein the source channel contact includes a first conductive layer and a second conductive layer;
• an upper stack including a plurality of dielectric layers and a plurality of gate electrodes alternately stacked over the lower stack;
• a channel layer penetrating the upper stack and extending in the lower stack, wherein the channel layer contacts with the source channel contact;
• a barrier oxide formed over the first and second conductive layers of the source channel contact;
• a vertical contact recess formed in the upper stack and extending to the barrier oxide;
• and
• a sealing spacer formed over a side wall of the vertical contact recess and extending to cover the barrier oxide,
• wherein the barrier oxide includes a non-planar surface in contact with the first and second conductive layers of the source channel contact, and a planar surface in contact with the sealing spacer.