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US 2025/0260408 A1Published application
Phase noise cancelling phase locked loop (pll)
AssigneeArizona Board of Regents on behalf of Arizona State University
InventorsSaeed ZEINOLABEDINZADEH, Waleed Ahmad
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Abstract
A phase noise cancellation technique to reduce phase noise and improve timing stability in a variety of electronic devices. The system and method include two phase locked loops (PLLs) in a cascaded configuration. The second PLL is used as a buffer to collect the replicated correlated phase noise which is then used in a feedback circuit to cancel out the original phase noise on the first PLL.
Claims20
A method for cancelling phase noise comprising:
- selecting a first bandwidth and a first voltage-controlled oscillator (VCO) for a first phase locked loop (PLL);
- selecting a second bandwidth and a second VCO for a second PLL;
- supplying a first reference signal and a first frequency divider signal as input to the first PLL, an output from the first PLL being an input to a first frequency divider, the first frequency divider producing the first frequency divider signal;
- supplying the first frequency divider signal as a second reference signal to the second PLL and a second frequency divider signal as input to the second PLL, an output from the second PLL being the input to a second frequency divider, the second frequency divider producing the second frequency divider signal;
- and
- cancelling the phase noise on a control node of the first VCO by subtracting a weighted amplified correlated noise voltage of a control node of the second VCO from a noise voltage of the control node of the first VCO after amplification by an amplifier.
3 more elements
A system for cancelling phase noise comprising:
- a first phase locked loop (PLL) having a first pre-selected bandwidth, the first PLL receiving a reference signal, the first PLL having a first voltage-controlled oscillator (VCO);
- a second PLL having a second pre-selected bandwidth, the second PLL having a second VCO;
- a first frequency divider supplying a first frequency divider signal as an input signal to the first PLL and the reference signal to the second PLL, the first frequency divider receiving an output signal from the first PLL as the input signal to the first frequency divider;
- and
- a second frequency divider receiving an output from the second PLL and supplying a second frequency divider signal to the second PLL,
- wherein the phase noise is cancelled on a control line of the first VCO by subtracting a correlated noise voltage of a control node of the second VCO from a noise voltage of the control node of the first VCO, the correlated noise voltage of the control node of the second VCO being amplified.
3 more elements
A method for cancelling noise in a first phase locked loop (PLL) comprising:
- using a second PLL as a buffer to the first PLL;
- collecting replicated correlated noise from the second PLL;
- and
- using a feedback circuit to cancel the noise of the first PLL.
1 more element
Dependencies are inferred from the claim text.