Memory device, method of manufacturing, and integrated circuit device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHuai-Ying HUANG, Yu-Ming LIN
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Abstract
A memory device includes a memory cell having a first transistor, a second transistor, a first capacitor and a second capacitor coupled with each other into a data storage circuit configured to store a datum. The memory cell further has a third transistor and a fourth transistor coupled with each other into a comparison circuit configured to perform a comparison of the datum stored in the data storage circuit with a search input datum. The memory device further includes a back-end-of-line (BEOL) structure. The BEOL structure includes at least a part of the memory cell.
Claims20
A memory device, comprising:
- a memory cell having
- a first transistor, a second transistor, a first capacitor and a second capacitor coupled with each other into a data storage circuit configured to store a datum, and
- a third transistor and a fourth transistor coupled with each other into a comparison circuit configured to perform a comparison of the datum stored in the data storage circuit with a search input datum;
- and
- a back-end-of-line (BEOL) structure, wherein the BEOL structure comprises at least a part of the memory cell.
A method, comprising:
- performing front-end-of-line (FEOL) processing to obtain FEOL circuitry over a substrate;
- and
- performing back-end-of-line (BEOL) processing to obtain a BEOL structure over the FEOL circuitry and the substrate, wherein
- the BEOL structure comprises a content-addressable memory (CAM) array.
An integrated circuit (IC) device, comprising:
- a substrate;
- front-end-of-line (FEOL) circuitry over the substrate;
- and
- a back-end-of-line (BEOL) structure over the FEOL circuitry,
- wherein the BEOL structure comprises:
- first and second capacitors,
- first and second active structures extending along a first direction, the first and second active structures spaced from each other along a second direction transverse to the first direction,
- first through fourth gate electrodes extending along the second direction, the first and fourth gate electrodes over the first active structure, and the second and third gate electrodes over the second active structure,
- a first interconnect structure coupling the third gate electrode to the first active structure and the first capacitor, and
- a second interconnect structure coupling the fourth gate electrode to the second active structure and the second capacitor.
Dependencies are inferred from the claim text.