Protocol For Refresh Between A Memory Controller And A Memory Device

A memory controller integrated circuit, comprising:

• an interface to couple the memory controller integrated circuit, via a conductive link, to a dynamic random access memory (DRAM) device having banks, including a first bank and a second bank;
• and
• logic to, via the interface, issue data access commands to the DRAM device, wherein the data access commands include commands addressed to a first one of the banks and commands addressed to a second one of the banks;
• wherein the logic is to sequence the issuance of the commands addressed to the second one of the banks, relative to issuance of the commands addressed to the first one of the banks, in a manner dependent on progress information, received from the DRAM device, indicating that the first one of the banks is undergoing a refresh operation.

A memory controller integrated circuit, comprising:

• a first interface to couple the memory controller integrated circuit, via a first conductive link, to a first set of banks of a dynamic random access memory (DRAM) device;
• a second interface to couple the memory controller integrated circuit, via a second conductive link, to a second set of banks of the DRAM device;
• logic to place the DRAM device into a selective one of a normal data transmission mode, in which the DRAM device is operable to transfer data between the first set of banks and the memory controller integrated circuit at a first data rate, and a low power mode, in which the DRAM device is disabled from transferring data between the first set of banks and the memory controller integrated circuit at the first data rate;
• and
• logic to, via the first interface, issue data access commands to first set of banks of the DRAM device, and via the second interface, issue data access commands to the second set of banks of the DRAM device, wherein the data access commands issued to the first set of banks include commands addressed to a first bank and wherein the data access commands issued to the second set of banks include commands addressed to a second bank;
• logic is to sequence the issuance of the commands addressed to the second bank, relative to issuance of the commands addressed to the first bank, in a manner dependent on progress information, received from the DRAM device, indicating that the first bank is undergoing a refresh operation in association with the low power mode.