Wafer-level design, manufacturing, and integration methods of system on wafer

A wafer-level design, manufacturing, and integration method of a system on wafer (SoW), comprising:

• an integrated functional/sensor devices (dies) bonding with multiple wafers, comprising a wafer (dies layer) with outer functional layer of the functional/sensor devices (dies), a wafer (dies layer) with middle functional layer of the functional/sensor devices (dies), and a wafer (dies layer) with inner functional layer of the functional/sensor devices (dies), wherein the wafers on an outer layer, a middle layer, and an inner layer bond into the functional/sensor devices (dies) with a high density, wherein the devices (dies) generated complete functions;
• an electrical interconnect layer, comprising RDLs on front and back surfaces and partitioned TSV arrays interconnect between the upper and lower surfaces;
• a back-end dies layer (wafer), comprising dies for computing, communication and storage, and power supply ports;
• and heat dissipation module layer, comprising serpentine liquid cooling channels, liquid cooling inlet/outlet ports, and a recessed patterned heat dissipation groove complementary on the back-end dies layer.