Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunsoo Chung, Jinchan Ahn
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a logic chip, a redistribution wiring structure, memory chips and a molding member. The logic chip includes a first substrate and a passive element on a portion of the first substrate. The redistribution wiring structure is on the logic chip, and is electrically connected to the passive element. The memory chips are sequentially stacked on the redistribution wiring structure in a vertical direction. The molding member is on the logic chip, and extends on sidewalls of the redistribution wiring structure and the memory chips. The passive element does not overlap the memory chips in the vertical direction.
Claims20
A semiconductor package comprising:
- a logic chip comprising a first substrate and a passive element on a portion of the first substrate;
- a redistribution wiring structure on the logic chip, the redistribution wiring structure being electrically connected to the passive element;
- memory chips sequentially stacked on the redistribution wiring structure in a vertical direction;
- and
- a molding member on the logic chip, the molding member extending on sidewalls of the redistribution wiring structure and the memory chips,
- wherein the passive element does not overlap the memory chips in the vertical direction.
A semiconductor package comprising:
- a logic die comprising:
- a substrate including first and second surfaces opposite to each other in a vertical direction;
- a through electrode structure extending through the substrate, the through electrode structure comprising a protrusion portion protruding beyond the second surface of the substrate;
- a protective pattern structure on the second surface of the substrate, the protective pattern structure extending on a sidewall of the protrusion portion of the through electrode structure;
- and
- a capacitor comprising a lower portion and an upper portion, the lower portion of the capacitor extending into a portion of the substrate adjacent to the second surface thereof, and the upper portion of the capacitor having the protective pattern structure thereon;
- a redistribution wiring structure on the logic die, the redistribution wiring structure being electrically connected to the capacitor;
- memory dies sequentially stacked on the redistribution wiring structure;
- and
- a molding member on the logic die, the molding member extending on sidewalls of the redistribution wiring structure and the memory dies,
- wherein each of the memory dies does not overlap the capacitor in the vertical direction.
A semiconductor package comprising:
- a buffer die comprising:
- a first substrate including first and second surfaces opposite to each other in a vertical direction;
- a logic device in the first substrate;
- a first wiring structure electrically connected to the logic device;
- a first through electrode structure extending through the first substrate in the vertical direction, the first through electrode structure including a first protrusion portion protruding beyond the second surface of the first substrate;
- a first protective pattern structure on the second surface of the first substrate, the first protective pattern structure extending on a sidewall of the first protrusion portion of the first through electrode structure;
- and
- a capacitor comprising a lower portion and an upper portion, the lower portion of the capacitor extending into a portion of the first substrate adjacent to the second surface thereof, and the upper portion of the capacitor having the first protective pattern structure thereon;
- a redistribution wiring structure on the buffer die, the redistribution wiring structure being electrically connected to the capacitor;
- core dies sequentially stacked on the redistribution wiring structure in the vertical direction;
- adhesion layers between the redistribution wiring structure and a lowermost one of the core dies, and between respective ones of the core dies that are sequentially stacked;
- and
- a molding member on the buffer die, the molding member extending on sidewalls of the redistribution wiring structure, the core dies, and the adhesion layers,
- wherein the capacitor does not overlap the core dies in the vertical direction.
Dependencies are inferred from the claim text.