Package structure and manufacturing method thereof
OwnerChung W. Hoinventor
Life of this patent
Estimating the term…
Abstract
A package structure includes a multi-layer circuit layer, multiple components, and a stress adjustment board. The multi-layer circuit layer has a first surface and a second surface opposite to each other. The components are configured on the first surface of the multi-layer circuit layer and electrically connected to the multi-layer circuit layer. The stress adjustment board is configured on the second surface of the multi-layer circuit layer. The stress adjustment board includes a copper layer and has multiple conductive vias. The conductive vias are electrically connected to the multi-layer circuit layer. A first peripheral surface of the multi-layer circuit layer is aligned with a second peripheral surface of the stress adjustment board.
Claims9
A package structure, comprising:
- a multi-layer circuit layer, having a first surface and a second surface opposite to each other;
- a plurality of components, configured on the first surface of the multi-layer circuit layer and electrically connected to the multi-layer circuit layer;
- and
- a stress adjustment board, configured on the second surface of the multi-layer circuit layer, wherein the stress adjustment board comprises no trace copper layers and dielectric layers and has a plurality of conductive vias, the plurality of conductive vias being electrically connected to the multi-layer circuit layer, wherein a first peripheral surface of the multi-layer circuit layer is aligned with a second peripheral surface of the stress adjustment board.
A manufacturing method of a package structure, comprising:
- forming a multi-layer circuit layer on a substrate, the multi-layer circuit layer having a first surface and a second surface opposite to each other, wherein the first surface of the multi-layer circuit layer is configured on the substrate;
- forming a stress adjustment board configured on the second surface of the multi-layer circuit layer, wherein the stress adjustment board comprises no trace copper and dielectric layers and has a plurality of conductive vias, the plurality of conductive vias being electrically connected to the multi-layer circuit layer, wherein a first peripheral surface of the multi-layer circuit layer is aligned with a second peripheral surface of the stress adjustment board;
- removing the substrate to expose the first surface of the multi-layer circuit layer;
- and
- configuring a plurality of components on the first surface of the multi-layer circuit layer, the plurality of components being electrically connected to the multi-layer circuit layer.
Dependencies are inferred from the claim text.