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US 2025/0226318 A1Published application
Component inter-digitated vias and leads
AssigneeMicron Technology, Inc.
InventorChristopher F. Kinney
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).
Claims20
(canceled)
A substrate for a memory sub-system comprising:
- a plurality of vias distributed upon the substrate, the plurality of vias comprising:
- a set of power vias including a first power via and a second power via;
- a set of ground vias;
- and
- a webbing between the first power via and the second power via.
2 more elements
A method for reducing inductance on an integrated circuit package comprising:
- distributing a plurality of vias upon a substrate, the plurality of vias comprising:
- a set of power vias including a first power via and a second power via;
- a set of ground vias;
- and
- a webbing between the first power via and the second power via.
2 more elements
Dependencies are inferred from the claim text.