Hybrid victim cache and write miss buffer with fence operation
AssigneeTexas Instruments Incorporated
InventorsNaveen BHORIA, Timothy David ANDERSON, Pete HIPPLEHEUSER
Life of this patent
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Abstract
A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.
Claims20
A system, comprising:
- a first sub-cache;
- and
- a second sub-cache corresponding to a cache level same as the first sub-cache and configured to:
- receive a first write memory command that is associated with a write miss in the first sub-cache, the first write memory command associated with a first eviction tag;
- store first data associated with the first write memory command in a cache line of the second sub-cache;
- store the first eviction tag to indicate that the first data is associated with a write miss in the first sub-cache;
- receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag;
- and
- merge the second eviction tag with the first eviction tag to generate a merged eviction tag.
A method, comprising:
- receiving, by a caching system, a first write memory command, wherein the caching system includes a first sub-cache and a second sub-cache corresponding to a cache level same as the first sub-cache, wherein the first write memory command is associated with a write miss in the first sub-cache, and wherein the first write memory command is associated with a first eviction tag;
- storing, by the second sub-cache, first data associated with the first write memory command in a cache line of the second sub-cache;
- storing, by the second sub-cache, the first eviction tag to indicate that the first data is associated with a write miss in the first sub-cache;
- receiving, by the caching system, a second write memory command for the cache line, wherein the second write memory command is associated with a second eviction tag;
- and
- merging, by the second sub-cache, the second eviction tag with the first eviction tag to generate a merged eviction tag.
A device, comprising:
- a processor;
- a first sub-cache coupled to the processor;
- and
- a second sub-cache corresponding to a cache level same as the first sub-cache and configured to:
- receive a first write memory command that is associated with a write miss in the first sub-cache, the first write memory command associated with a first eviction tag;
- store first data associated with the first write memory command in a cache line of the second sub-cache;
- store the first eviction tag to indicate that the first data is associated with a write miss in the first sub-cache;
- receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag;
- and
- merge the second eviction tag with the first eviction tag to generate a merged eviction tag.
Dependencies are inferred from the claim text.