Memory device including interface circuit and operating method thereof

An operating method of a memory device, the memory device comprising an interface circuit and a plurality of memory chips, the operating method comprising:

• receiving a clock signal and a command/address signal from a memory controller;
• reading some data of a second memory chip from among the plurality of memory chips in advance while reading data of a first memory chip from among the plurality of memory chips based on the command/address signal;
• and
• storing the read some data of the second memory chip in the interface circuit.

A memory system comprising:

• a memory device comprising a plurality of non-volatile memory chips and an interface circuit, the interface circuit comprising a plurality of first-in first-out (FIFO) registers respectively corresponding to the plurality of non-volatile memory chips;
• and
• a memory controller connected to the interface circuit, the memory controller configured to transmit and receive data,
• wherein the memory device is configured to read some data of a second non-volatile memory chip from among the plurality of non-volatile memory chips in advance and to store the read some data in a target FIFO register from among the plurality of FIFO registers while reading data of a first non-volatile memory chip from among the plurality of non-volatile memory chips, and the target FIFO register is a FIFO register from among the plurality of FIFO registers corresponding to the second non-volatile memory chip.