# US 2025/0221069 A1 · Cmos image sensing device

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- Number: US 2025/0221069 A1
- Document ID: US20250221069A1
- Status: Published application
- Kind: A1
- Application number: 18/931,829
- Filed: 2024-10-30
- Published: 2025-07-03
- Earliest claimed: 2023-12-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hwanwoong KIM; Hyuncheol KIM
- Web page: https://patentgrep.com/patent/US20250221069A1

## CPC

- H10F 39/80373: {characterised by the gate of the transistor}
- H10F 39/807: {Pixel isolation structures}
- H04N 25/51: Control of the gain
- H04N 25/57: Control of the dynamic range
- H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- H10F 39/014: {of CMOS image sensors}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/80377: {characterised by the channel of the transistor, e.g. channel having a doping gradient}
- H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

An image sensing device includes: a substrate; and a plurality of pixels isolated by an insulating film disposed within the semiconductor substrate. The plurality of pixels share a first active region, wherein at least one of the plurality of pixels comprises a photoelectronic conversion element and a transfer transistor. The photoelectronic conversion element is connected to the first active region by the transfer transistor. The first active region and a first floating diffusion region are connected by the transfer transistor. The first floating diffusion region is connected to a gate of a source follower transistor, and the first floating diffusion region is connected to a second floating diffusion region through a first transistor. The first transistor is turned off when an operating mode is a first mode. The first transistor is turned on when the operating mode is a second mode different from the first mode.

## Claims

### Claim 1

A complementary metal-oxide-semiconductor (CMOS) image sensing device comprising:
a semiconductor substrate including a plurality of pixel regions;
an insulating film disposed within the semiconductor substrate and disposed between the plurality of pixel regions; and
a first active region disposed between the plurality of pixel regions,
wherein a photoelectronic conversion element and a transfer transistor are disposed in at least one of the plurality of pixel regions,
wherein the photoelectronic conversion element is connected to the first active region by the transfer transistor,
wherein the first active region and a first floating diffusion region are connected by at least one of the transfer transistors,
wherein the first floating diffusion region is connected to a gate of a source follower transistor, and the first floating diffusion region is connected to a second floating diffusion region through a first transistor, and
wherein the first transistor is turned off when an operating mode is a first mode, and the first transistor is turned on when the operating mode is a second mode different from the first mode.

### Claim 2 (depends on 1)

The CMOS image sensing device of claim 1, wherein the second floating diffusion region is connected to a reset transistor, and
wherein the source follower transistor is connected to a selection transistor.

### Claim 3 (depends on 2)

The CMOS image sensing device of claim 2, wherein a gate extension in the gate of the source follower transistor is connected to the first floating diffusion region across the insulating film.

### Claim 4 (depends on 1)

The CMOS image sensing device of claim 1, wherein the insulating film is configured to penetrate a substrate or is a deep trench isolation (DTI).

### Claim 5 (depends on 1)

The CMOS image sensing device of claim 1, wherein a conversion gain of at least one pixel provided by the plurality of pixel regions in the first mode is greater than a conversion gain of at least one pixel provided by the plurality of pixel regions in the second mode.

### Claim 6 (depends on 1)

The CMOS image sensing device of claim 1, wherein the plurality of pixel regions are four pixel regions providing four pixels.

### Claim 7 (depends on 6)

The CMOS image sensing device of claim 6, wherein the four pixels are configured to operate as a single pixel in the first mode.

### Claim 8 (depends on 6)

The CMOS image sensing device of claim 6, wherein the four pixels are configured to operate as individual pixels in the second mode.

### Claim 9 (depends on 6)

The CMOS image sensing device of claim 6, wherein the insulating film does not extend to a corner shared by the four pixel regions, and
wherein the first active region shared by the four pixel regions is located in the corner shared by the four pixel regions.

### Claim 10 (depends on 3)

The CMOS image sensing device of claim 3, wherein the gate extension in the gate of the source follower transistor substantially contacts the first floating diffusion region, and
wherein a gate oxide film is between the semiconductor substrate and at least a portion of the gate of the source follower transistor, and
wherein at least the portion of the gate of the source follower transistor is different from the gate extension.

### Claim 11 (depends on 3)

The CMOS image sensing device of claim 3, wherein the gate of the source follower transistor is connected to the first floating diffusion region by wirings.

### Claim 12 (depends on 1)

The CMOS image sensing device of claim 1, wherein the gate of the transfer transistor is a dual vertical gate.

### Claim 13 (depends on 1)

The CMOS image sensing device of claim 1, wherein the gate of the source follower transistor is a Fin Field-Effect Transistor (FinFET) type gate.

### Claim 14 (depends on 1)

The CMOS image sensing device of claim 1, wherein at least one of the plurality of pixel regions comprises a node for applying a predetermined bias voltage to the semiconductor substrate, and
wherein the node is connected to an adjacent gate.

### Claim 15 (depends on 1)

The CMOS image sensing device of claim 1, wherein the first active region comprises a floating diffusion region.

### Claim 16 (depends on 15)

The CMOS image sensing device of claim 15, wherein a doping concentration of N-type impurities of the first floating diffusion region is greater than a doping concentration of N-type impurities of the floating diffusion region in the first active region.

### Claim 17 (depends on 15)

The CMOS image sensing device of claim 15, wherein a potential of the first floating diffusion region is lower than a potential of the floating diffusion region in the first active region.

### Claim 18 (depends on 15)

The CMOS image sensing device of claim 15, wherein an area of the floating diffusion region in the first active region is greater than an area of the first floating diffusion region.

### Claim 19

(canceled)

### Claim 20 (depends on 1)

The CMOS image sensing device of claim 1, wherein the plurality of pixel regions provide one cluster pixel, and other plurality of pixel regions adjacent to the plurality of pixels provide the other cluster pixel,
wherein a number of the plurality of pixel regions is equal to a number of the other plurality of pixel regions,
wherein a second active region is disposed between the other plurality of pixel regions, and
wherein the first active region and the second active region are connected by wirings.

### Claim 21

An image sensor comprising:
a reset transistor connected to a pixel bias voltage node configured to supply a pixel bias voltage;
first to fourth transfer transistors connected between first to fourth photodiodes and a floating diffusion region, respectively;
a first transistor connected between the floating diffusion region and the reset transistor;
a source follower transistor connected to the floating diffusion region; and
a selection transistor connected between the source follower transistor and a column line,
wherein the reset transistor is turned on and the first transistor is turned off during a turn-on time of the selection transistor in a first mode, and the reset transistor is turned off and the first transistor is turned on during a turn-on time of the selection transistor in a second mode, and
wherein a conversion gain in the second mode is less than a conversion gain in the first mode.

### Claim 22

(canceled)

### Claim 23

(canceled)