# US 2025/0220902 A1 · Consolidation of staircase area etch and cmos contact area etch in 3d nand > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0220902 A1 - Document ID: US20250220902A1 - Status: Published application - Kind: A1 - Application number: 18/851,045 - Filed: 2022-04-27 - Published: 2025-07-03 - Earliest claimed: 2022-04-27 - Assignees: Intel NDTM US LLC - Applicants: Intel NDTM US LLC - Inventors: Liu Liu; Chuan Sun; Jianze Zhao - Web page: https://patentgrep.com/patent/US20250220902A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems, apparatuses, and methods may provide for technology that simultaneously forms staircase areas and CMOS (complementary metal-oxide-semiconductor) contact areas in three-dimensional (3D) NAND memory. A 3D NAND memory includes a first CMOS contact area and a first staircase area. The first CMOS contact area is formed through a plurality of sequential chops. The first staircase area is formed through a plurality of sequential staircase chops. The first CMOS contact area is formed through the plurality of sequential chops being performed simultaneous to the plurality of sequential staircase chops. ## Claims ### Claim 1 A memory device comprising: a memory array; and a memory block coupled to the memory array, the memory block comprising: a first complementary metal-oxide-semiconductor contact area, wherein the first complementary metal-oxide-semiconductor contact area has been formed through a plurality of sequential chops. ### Claim 2 (depends on 1) The memory device of claim 1, the memory block further comprising: a first staircase area, wherein the first staircase area has been formed through a plurality of sequential staircase chops, and wherein the first complementary metal-oxide-semiconductor contact area has been formed through the plurality of sequential chops performed simultaneous to the plurality of sequential staircase chops. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the first complementary metal-oxide-semiconductor contact area includes one or more side walls defining a central opening, and wherein the one or more side walls have a nitride stop layer deposited thereon. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the first staircase area includes one or more staircase walls defining a staircase opening, and wherein the one or more staircase walls have the nitride stop layer deposited thereon. ### Claim 5 (depends on 3) The memory device of claim 3, wherein the one or more side walls have the nitride stop layer deposited thereon in a plurality of separately performed depositions. ### Claim 6 (depends on 2) The memory device of claim 2, wherein contacts formed in the first complementary metal-oxide-semiconductor contact area and the first staircase area were formed simultaneously. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the memory device is a three-dimensional (3D) NAND memory. ### Claim 8 A solid state drive (SSD) comprising: a memory controller; and a memory device coupled to the memory controller, the memory device comprising: a memory array; and a memory block coupled to the memory array, the memory block comprising: a first complementary metal-oxide-semiconductor contact area, wherein the first complementary metal-oxide-semiconductor contact area has been formed through a plurality of sequential chops. ### Claim 9 (depends on 8) The solid state drive (SSD) of claim 8, the memory block further comprising: a first staircase area, wherein the first staircase area has been formed through a plurality of sequential staircase chops, and wherein the first complementary metal-oxide-semiconductor contact area has been formed through the plurality of sequential chops performed simultaneous to the plurality of sequential staircase chops. ### Claim 10 (depends on 8) The solid state drive (SSD) of claim 8, wherein the first complementary metal-oxide-semiconductor contact area includes one or more side walls defining a central opening, and wherein the one or more side walls have a nitride stop layer deposited thereon. ### Claim 11 (depends on 10) The solid state drive (SSD) of claim 10, wherein the first staircase area includes one or more staircase walls defining a staircase opening, and wherein the one or more staircase walls have the nitride stop layer deposited thereon. ### Claim 12 (depends on 10) The solid state drive (SSD) of claim 10, wherein the one or more side walls have the nitride stop layer deposited thereon in a plurality of separately performed depositions. ### Claim 13 (depends on 9) The solid state drive (SSD) of claim 9, wherein contacts formed in the first complementary metal-oxide-semiconductor contact area and the first staircase area were formed simultaneously. ### Claim 14 A method comprising: forming a multi-deck structure; and performing a plurality of sequential chops to the multi-deck structure to form a central opening of a first complementary metal-oxide-semiconductor contact area. ### Claim 15 (depends on 14) The method of claim 14, further comprising: performing a plurality of sequential staircase chops to the multi-deck structure to form a staircase opening of a first staircase area, wherein the plurality of sequential chops is performed simultaneous to the plurality of sequential staircase chops. ### Claim 16 (depends on 15) The method of claim 15, further comprising: depositing a nitride stop layer on one or more staircase walls of the first staircase area and on one or more side walls of the first complementary metal-oxide-semiconductor contact area, wherein the nitride stop layer is deposited after completion of the staircase opening. ### Claim 17 (depends on 16) The method of claim 16, further comprising: performing an additional chop to remove residual material in the central opening of the first complementary metal-oxide-semiconductor contact area while the staircase opening of the first staircase area is protected by a photoresist fill. ### Claim 18 (depends on 17) The method of claim 17, further comprising: depositing an additional nitride stop layer on the one or more side walls of the first complementary metal-oxide-semiconductor contact area, wherein the additional nitride stop layer is deposited after removal of the residual material in the central opening. ### Claim 19 (depends on 18) The method of claim 18, further comprising: performing a gap fill and performing a chemical mechanical polish for the central opening and the staircase opening simultaneously. ### Claim 20 (depends on 19) The method of claim 19, further comprising: performing a contact etch and fill for the first complementary metal-oxide-semiconductor contact area and the first staircase area simultaneously.