# US 2025/0218924 A1 · Electroless nickel-electroless palladium-immersion gold (enepig) as a surface finish for embedded die attachments

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- Number: US 2025/0218924 A1
- Document ID: US20250218924A1
- Status: Published application
- Kind: A1
- Application number: 18/400,878
- Filed: 2023-12-29
- Published: 2025-07-03
- Earliest claimed: 2023-12-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Prithwish Chatterjee; Shruti Sharma; Numair Ahmed; Yuxin Fang; Wei-Lun Jen; Siddharth Alur Narasimha Krishna; Mollie A. Stewart; Srinivas Venkata Ramanuja Pietambaram; Suresh T. Narute
- Web page: https://patentgrep.com/patent/US20250218924A1

## CPC

- H10W 70/66: Conductive materials thereof
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/072: {of bump connectors}
- H10W 72/07255: {changes in materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2528: {Intermetallic compounds}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

## Claims

### Claim 1

An integrated circuit package substrate comprising:
a plurality of metallization layers in dielectric buildup layers;
a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and
conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising nickel, phosphorous, tin, and palladium.

### Claim 2 (depends on 1)

The integrated circuit package substrate of claim 1, wherein the conductive materials comprise an intermetallic compound comprising nickel and phosphorous.

### Claim 3 (depends on 2)

The integrated circuit package substrate of claim 2, wherein the intermetallic compound comprises phosphorous at between 15-30% by weight.

### Claim 4 (depends on 1)

The integrated circuit package substrate of claim 1, wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.

### Claim 5 (depends on 4)

The integrated circuit package substrate of claim 4, wherein the intermetallic compound comprises copper at between 20-40% by weight, nickel at between 20-40% by weight, and tin at between 30-50% by weight.

### Claim 6 (depends on 1)

The integrated circuit package substrate of claim 1, wherein the conductive materials comprise an intermetallic compound comprising nickel, tin, and phosphorous.

### Claim 7 (depends on 1)

The integrated circuit package substrate of claim 1, wherein the conductive materials comprise a layer on the conductive pads of the metallization layer comprising nickel and phosphorous.

### Claim 8 (depends on 1)

The integrated circuit package substrate of claim 1, wherein the die is an interconnect bridge circuitry die.

### Claim 9 (depends on 8)

The integrated circuit package substrate of claim 8, wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.

### Claim 10 (depends on 1)

The integrated circuit package substrate of claim 1, wherein the die is encapsulated in a cavity or opening in the buildup layers.

### Claim 11

An integrated circuit package comprising:
an integrated circuit package substrate comprising:
a plurality of metallization layers in dielectric buildup layers;
an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and
conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising nickel, phosphorous, tin, and palladium; and
integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.

### Claim 12 (depends on 11)

The integrated circuit package of claim 11, wherein the conductive materials comprise an intermetallic compound comprising nickel and phosphorous.

### Claim 13 (depends on 12)

The integrated circuit package of claim 12, wherein the intermetallic compound comprises phosphorous at between 15-30% by weight.

### Claim 14 (depends on 11)

The integrated circuit package of claim 11, wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.

### Claim 15 (depends on 14)

The integrated circuit package of claim 14, wherein the intermetallic compound comprises copper at between 20-40% by weight, nickel at between 20-40% by weight, and tin at between 30-50% by weight.

### Claim 16 (depends on 11)

The integrated circuit package of claim 11, wherein the conductive materials comprise an intermetallic compound comprising nickel, tin, and phosphorous.

### Claim 17 (depends on 11)

The integrated circuit package of claim 11, wherein the second conductive contact of the interconnect bridge circuitry die has a thickness between 5-12 um.

### Claim 18

A method of forming an integrated circuit package substrate comprising:
forming buildup layers on a core layer, the buildup layers comprising a plurality of metallization layers;
forming a cavity in the buildup layers to expose a subset of conductive contacts of a metallization layer;
forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer comprising nickel and having a thickness that is greater than 5 um;
forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium;
forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold;
placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first surface finish layer is formed using electroless plating, the second surface finish layer is formed using electroless plating, and the third surface finish layer is formed using immersion plating.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first surface finish layer is between 5-10 um thick, the second surface finish layer is between 0.01-0.10 μm thick, and the third surface finish layer is between 0.01-0.10 μm thick.