# US 2025/0218902 A1 · Semiconductor structure and fabrication method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0218902 A1 - Document ID: US20250218902A1 - Status: Published application - Kind: A1 - Application number: 18/423,309 - Filed: 2024-01-26 - Published: 2025-07-03 - Earliest claimed: 2023-12-29 - Assignees: United Microelectronics Corp. - Applicants: United Microelectronics Corp. - Inventors: Chu-Fu Lin; Chuan-Lan Lin; Yu-Ping Wang; Chun-Hung Chen - Web page: https://patentgrep.com/patent/US20250218902A1 ## CPC - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 72/90: Bond pads, in general - H10W 90/00: Package configurations - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor structure includes a bottom wafer having a bottom substrate and a bottom interconnect structure on the bottom substrate, and a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate. The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer. An oxide-nitride-oxide (ONO) dielectric layer covers the rear surface of the top substrate. A plurality of conductive vias is disposed on the rear surface and extending into the ONO dielectric layer and the top substrate. ## Claims ### Claim 1 A semiconductor structure, comprising: a bottom wafer comprising a bottom substrate and a bottom interconnect structure on the bottom substrate; a top wafer having a top substrate with a front surface and a rear surface, and a top interconnect structure disposed on the front surface of the top substrate, wherein the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; and a plurality of conductive vias disposed on the rear surface and extending into the ONO dielectric layer and the top substrate. ### Claim 2 (depends on 1) The semiconductor structure according to claim 1, wherein the top substrate comprises a silicon substrate and has a thickness of about 3-5 micrometers. ### Claim 3 (depends on 1) The semiconductor structure according to claim 1, wherein the plurality of conductive vias is electrically connected to the top interconnect structure disposed on the front surface of the top substrate. ### Claim 4 (depends on 1) The semiconductor structure according to claim 1, wherein the plurality of conductive vias comprises copper or aluminum. ### Claim 5 (depends on 1) The semiconductor structure according to claim 1, wherein the plurality of conductive vias has a top surface that is coplanar with a top surface of the ONO dielectric layer. ### Claim 6 (depends on 1) The semiconductor structure according to claim 1, wherein the bottom wafer has a first vertical sidewall and the top wafer has a second vertical sidewall, and wherein the first vertical sidewall is flush with the second vertical sidewall. ### Claim 7 (depends on 6) The semiconductor structure according to claim 6, wherein the bottom wafer has an edge portion that protrudes from the first vertical sidewall. ### Claim 8 (depends on 7) The semiconductor structure according to claim 7, wherein the first vertical sidewall and the second vertical sidewall are covered with a protective layer. ### Claim 9 (depends on 8) The semiconductor structure according to claim 8, wherein the protective layer extends onto an upper surface of the edge portion. ### Claim 10 (depends on 8) The semiconductor structure according to claim 8, wherein the protective layer comprises silicon oxide. ### Claim 11 A method of forming a semiconductor structure, comprising: providing a bottom wafer comprising a bottom substrate and a bottom interconnect structure on the bottom substrate; providing a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate, wherein the top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer; forming an oxide-nitride-oxide (ONO) dielectric layer covering the rear surface of the top substrate; and after forming the ONO dielectric layer, forming a plurality of conductive vias on the rear surface and extending into the ONO dielectric layer and the top substrate. ### Claim 12 (depends on 11) The method according to claim 11, wherein the top substrate comprises a silicon substrate and has a thickness of about 3-5 micrometers. ### Claim 13 (depends on 11) The method according to claim 11, wherein the plurality of conductive vias is electrically connected to the top interconnect structure disposed on the front surface of the top substrate. ### Claim 14 (depends on 11) The method according to claim 11, wherein the plurality of conductive vias comprises copper or aluminum. ### Claim 15 (depends on 11) The method according to claim 11, wherein the plurality of conductive vias has a top surface that is coplanar with a top surface of the ONO dielectric layer. ### Claim 16 (depends on 11) The method according to claim 11, wherein the bottom wafer has a first vertical sidewall and the top wafer has a second vertical sidewall, and wherein the first vertical sidewall is flush with the second vertical sidewall. ### Claim 17 (depends on 16) The method according to claim 16, wherein the bottom wafer has an edge portion that protrudes from the first vertical sidewall. ### Claim 18 (depends on 17) The method according to claim 17, wherein the first vertical sidewall and the second vertical sidewall are covered with a protective layer. ### Claim 19 (depends on 18) The method according to claim 18, wherein the protective layer extends onto an upper surface of the edge portion. ### Claim 20 (depends on 18) The method according to claim 18, wherein the protective layer comprises silicon oxide.