US 2025/0217181 A1 · THERMAL-AWARE INTERRUPT ROUTING IN AN INTERRUPT CONTROLLER IN PROCESSOR-BASED SYSTEMS, AND RELATED METHODS

Abstract

Thermal-aware interrupting routing in an interrupt controller in processor-based systems, and related methods are disclosed. The processor-based system includes one or more interrupt controllers that are each configured to prioritize interrupts received from components in the processor-based system and direct each received interrupt to a CPU core(s) in its designated processor to perform an interrupt service routine (ISR) to process the interrupt. To avoid or reduce the likelihood of the interrupt controller directing an interrupt to a CPU core(s) and/or CPU core cluster(s) that may exceed its thermal limit by accepting and handling the interrupt, the interrupt controller is configured to be aware of temperatures of the CPU cores and/or the CPU core clusters in its designated processor. The interrupt controller is configured to selectively route received interrupts based on temperature of the CPU core(s) and/or their CPU core cluster(s) that were determined eligible to receive and handle the interrupt.

Claims30

Dependent claims

An interrupt controller in a processor-based system, the interrupt controller configured to:

receive temperature data related to a temperature for a plurality of central processing units (CPU) cores in a processor in the processor-based system;
receive an interrupt in the processor-based system;
determine one or more eligible CPU cores of the plurality of CPU cores eligible to handle the interrupt based on an interrupt routing policy;
determine, based on the temperature data, a first set of eligible CPU cores of the one or more eligible CPU cores that would remain below a temperature threshold based on handling the interrupt;
and
communicate the interrupt to be received by the first set of eligible CPU cores.

3 more elements

A processor-based system, comprising:

a plurality of interrupt generating devices each configured to generate an interrupt;
a first processor comprising a plurality of first central processing unit (CPU) cores;
and
a first interrupt controller configured to:
receive first temperature data related to a temperature for the plurality of first CPU cores from one or more temperature sensors;
receive a first interrupt from an interrupt generating device of the plurality of interrupt generating devices;
determine one or more first eligible CPU cores of the plurality of first CPU cores eligible to handle the first interrupt based on a first interrupt routing policy;
determine, based on the first temperature data, a first set of eligible CPU cores of the one or more first eligible CPU cores that would remain below a first temperature threshold based on handling the first interrupt;
and
communicate the first interrupt to be received by the first set of eligible CPU cores;
and
each first eligible CPU core of the first set of eligible CPU cores configured to:
receive the first interrupt;
determine whether to service the first interrupt;
and
in response to determining to service the first interrupt, service the first interrupt.

13 more elements

Dependencies are inferred from the claim text.

Thermal-aware interrupt routing in an interrupt controller in processor-based systems, and related methods

Life of this patent

Thermal-aware interrupt routing in an interrupt controller in processor-based systems, and related methods

Life of this patent

Abstract

Claims30