# US 2025/0211237 A1 · Dfe-based peaking techniques for high-speed transmitters

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- Number: US 2025/0211237 A1
- Document ID: US20250211237A1
- Status: Published application
- Kind: A1
- Application number: 18/395,286
- Filed: 2023-12-22
- Published: 2025-06-26
- Earliest claimed: 2023-12-22
- Assignees: Avago Technologies International Sales Pte. Limited
- Applicants: Avago Technologies International Sales Pte. Limited
- Inventors: Arvindh Iyer; Anand J. Vasani
- Web page: https://patentgrep.com/patent/US20250211237A1

## CPC

- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H04L 25/028: {Arrangements specific to the transmitter end}
- H03K 17/6872: {using complementary field-effect transistors}
- H04B 1/04: Circuits
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04B: TRANSMISSION

## Abstract

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

## Claims

### Claim 1

A circuit comprising:
a serializer configured to combine multiple signals into one input signal to drive a forward inverter, the forward inverter being coupled to a first node and characterized by a first impedance in a serial configuration and a first capacitance in a parallel configuration;
a chain of inverters coupled in series from the first node to a m-th node with each n-th inverter being followed after n-th node and configured to transfer the input signal to the last node based on a signal transfer function, where n is an integer variable from 1 to m;
a first feedback inverter coupled from at least a third node along the chain to the first node to form a first feedback loop, the first feedback loop including two inverters after the first node and being configured to increase bandwidth by adding peaking response of the signal transfer function at the first node and the third node; and
a switch coupled to the m-th node.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the chain of inverters comprises four inverters sequentially with a first inverter, a second inverter, a third inverter, and a fourth inverter, the first inverter being coupled between the first node and a second node, the second inverter being coupled between the second node and the third node, the third inverter being coupled between the third node and a fourth node, the fourth inverter being coupled between the fourth node and a fifth node, where m=5.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the first feedback loop is characterized by a first time-constant τ associated with the first inverter coupled to the second inverter in the chain of inverters included in the feedback loop, wherein τ increases its value by adding more inverters in the chain of inverters included in the feedback loop.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the first feedback inverter is configured to provide a zero at (1/τ) in the signal transfer function at the first node.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the first feedback inverter is configured to reduce the signal transfer function at the third node to a single-pole response by canceling one pole at (1/τ).

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the first feedback inverter is characterized by a transconductance gm, wherein impedance at the first node is a function of 1/gm, and is configured to reduce DC gain of the impedance at the first node and increase peaking amount at high frequencies in the signal transfer function at the first node and the third node, hereby increasing bandwidth.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the first feedback inverter comprises a current-starved invertor comprising a first PMOS transistor and a second PMOS transistor having a first common source terminal, a first NMOS transistor and a second NMOS transistor having a second common source terminal, the first PMOS transistor and a first NMOS transistor having a first common drain terminal configured to be a first differential output terminal, the second PMOS transistor and a second NMOS transistor having a second common drain terminal configured to be a second differential output terminal, the first PMOS transistor and the first NMOS transistor having a first common gate terminal configured to be a first differential input terminal, the second PMOS transistor and the second NMOS transistor having a second common gate terminal configured to be a second differential input terminal, the first common source terminal being coupled to a source voltage VDD via a third PMOS transistor with a first gate controlled by a first voltage and the second common source terminal being coupled to ground via a third NMOS transistor with a second gate controlled by a second voltage, the current-starved invertor being degenerated by the third PMOS transistor connecting the source VDD to first common source terminal and the third NMOS transistor connecting the second common source terminal to the ground to reduce transistor aging caused by hot-carrier injection.

### Claim 8 (depends on 7)

The circuit of claim 7, wherein the first voltage and the second voltage are varied based on an additive complementary to the source voltage VDD for tuning bias currents flown respectively from a source to the first common source terminal and from the second common source terminal to ground.

### Claim 9 (depends on 7)

The circuit of claim 7, wherein the first voltage and the second voltage are independently varied for adjusting peaking amount in frequency response of the signal transfer function.

### Claim 10 (depends on 2)

The circuit of claim 2, further comprising a second feedback inverter coupled to the third node to form a second feedback loop driven from the fifth node along the chain with two inverters after the third node, the second feedback loop being characterized by a second time-constant and configured to add peaking amount in frequency response of the signal transfer functions at the third node and the fifth node.

### Claim 11

A device comprising:
an input inverter configured to receive an input signal from an output of a transmission stage, the input inverter having a first output impedance coupled in series to a first node and a first capacitance coupled in parallel to the first node;
a plurality of inverters coupled in a serial chain and configured to drive the input signal based on a signal transfer function from the first node to an output node; and
a feedback inverter coupled between the first node and at least the third node in the serial chain after two inverters to form a feedback loop, the feedback loop being configured to increase bandwidth by adding peaking amount in frequency response of the signal transfer function.

### Claim 12 (depends on 11)

The device of claim 11, wherein the plurality of inverters comprises a first inverter, a second inverter, a third inverter, and a fourth inverter, the first inverter being coupled between the first node and a second node, the second inverter being coupled between the second node and the third node, the third inverter being coupled between the third node and a fourth node, the fourth inverter being coupled between the fourth node and the output node.

### Claim 13 (depends on 11)

The device of claim 11, wherein the feedback loop is characterized by a time-constant τ that is configured to increase its value by adding more inverters in the serial chain that is included in the feedback loop.

### Claim 14 (depends on 13)

The device of claim 13, wherein the feedback inverter is configured to provide a zero at (1/τ) in the signal transfer function at the first node and cancel a pole at (1/τ) in the signal transfer function at the third node.

### Claim 15 (depends on 11)

The device of claim 11, wherein the first feedback inverter is characterized by a transconductance gm and is configured to reduce DC gain of impedance at the first node, wherein the impedance at the first node is a function of 1/gm, and increase peaking amount at high frequencies in the signal transfer function at the first node and the third node, hereby increasing bandwidth.

### Claim 16 (depends on 11)

The device of claim 11, wherein the feedback inverter comprises a pair of PMOS transistors with a first common source terminal and a pair of NMOS transistors with a second common source terminal, a first one of the pair of PMOS transistors being coupled to a first one of the pair of NMOS transistors at a first common drain terminal configured as a first differential output coupled to the first node and having a first common gate terminal configured to receive a first differential input from the third node, a second one of the pair of PMOS transistors being coupled to a second one of the pair of NMOS transistors at a second common drain terminal configured as a second differential output coupled to the first node and having a second common gate terminal configured to receive a second differential input from the third node.

### Claim 17 (depends on 16)

The device of claim 16, wherein the feedback inverter further comprises a third PMOS transistor having a drain terminal coupled to the first common source terminal and a source terminal coupled to a source voltage and a third NMOS transistor having a drain terminal coupled to the second common source terminal and a source terminal coupled to ground, the third PMOS transistor having a gate terminal provided by a first control voltage, the third NMOS transistor having a gate terminal provided by a second control voltage, the feedback invertor being degenerated by the third PMOS transistor connecting to the source voltage and the third NMOS transistor connecting to the ground to reduce transistor aging caused by hot-carrier injection.

### Claim 18 (depends on 17)

The device of claim 17, wherein the first control voltage and the second control voltage are adjustable with a limit that the first control voltage and the second control voltage are additive complementary to the source voltage VDD for tuning bias currents flown respectively from a source to the first common source terminal and from the second common source terminal to ground.

### Claim 19 (depends on 17)

The device of claim 17, wherein the first control voltage and the second control voltage are independently tuned to program the bias currents to control peaking amount in frequency response of the signal transfer function added by the feedback inverter.

### Claim 20 (depends on 11)

The device of claim 11, further comprising a second feedback inverter coupled between the third node and the output node in the serial chain to form a second feedback loop to increase bandwidth by adding peaking amount in frequency response of the signal transfer function at the third node.