# US 2025/0208902 A1 · Device, method and system to provide prediction state information of a processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0208902 A1 - Document ID: US20250208902A1 - Status: Published application - Kind: A1 - Application number: 18/396,415 - Filed: 2023-12-26 - Published: 2025-06-26 - Earliest claimed: 2023-12-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Ke Sun; Alyssa Milburn; Henrique De Medeiros Kawakami; Jason W. Brandt; Thais Moreira Hamasaki - Web page: https://patentgrep.com/patent/US20250208902A1 ## CPC - G06F 9/485: {Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence)} - G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer} - G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables} - G06F 9/3848: {using hybrid branch prediction, e.g. selection between prediction techniques} - G06F 9/3863: {using multiple copies of the architectural state, e.g. shadow registers} - G06F 9/461: {Saving or restoring of program or task context} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques and mechanisms for automatically saving and recovering microarchitectural prediction state information of a processor core. In an embodiment, a core comprises prediction circuitry which generates microarchitectural prediction state information based on an execution of a software process by the core. A prediction state manager of the processor detects a context switch of the processor and, based on such detection, automatically saves a version of the microarchitectural prediction state information to a repository which is external to the core. The microarchitectural prediction state information is available to be recovered from the repository to facilitate a resumed execution of the software process. In another embodiment, the microarchitectural prediction state information is saved to, or recovered from, the repository independent of an instruction of the software process, if any, which specifies that such saving or recovery is to be performed. ## Claims ### Claim 1 A processor comprising: a first execution engine of a first core, the first execution engine to perform an execution of a first software process; first prediction circuitry of the first core, the first prediction circuitry to generate first microarchitectural prediction state information based on the execution; and first prediction state manager circuitry coupled to the first prediction circuitry, the first prediction state manager circuitry to: receive a first indication of a first context switch which is to stop the execution of the first software process with the first core; and save a version of the first microarchitectural prediction state information, based on the first indication, to a repository which is external to the first core. ### Claim 2 (depends on 1) The processor of claim 1, wherein the first prediction state manager circuitry is further to: receive a second indication of a second context switch which is to resume the execution of the first software process; and recover the first microarchitectural prediction state information from the repository based on the second indication. ### Claim 3 (depends on 1) The processor of claim 1, wherein the first prediction state manager circuitry is to automatically save the version of the first microarchitectural prediction state information independent of any explicit software instruction. ### Claim 4 (depends on 1) The processor of claim 1, wherein the processor comprises the repository. ### Claim 5 (depends on 1) The processor of claim 1, wherein: the processor is to be coupled to a random access memory; and a portion of the random access memory is to comprise the repository. ### Claim 6 (depends on 1) The processor of claim 1, wherein the first prediction circuitry comprises one of a conditional branch predictor, an indirect branch predictor, a branch target buffer, or a return predictor. ### Claim 7 (depends on 1) The processor of claim 1, further comprising a cryptographic engine to perform an encryption process to generate the version of the first microarchitectural prediction state information. ### Claim 8 (depends on 1) The processor of claim 1, wherein the first core further comprises a context tagger circuit to tag the version of the first microarchitectural prediction state information with tag information which identifies the first software process. ### Claim 9 (depends on 1) The processor of claim 1, wherein the first prediction state manager circuitry is to save the version of the first microarchitectural prediction state information to the repository based on an operational mode of the processor, wherein the operational mode is to selectively enable the processor to save microarchitectural state of the first prediction circuitry. ### Claim 10 A method comprising: receiving a first indication of a first context switch by a processor, wherein the first context switch is to stop an execution of a first software process with a first core of the processor, wherein first prediction circuitry of the first core generates first microarchitectural prediction state information based on the execution of the first software process; and based on the first indication, automatically saving a version of the first microarchitectural prediction state information to a repository which is external to the first core. ### Claim 11 (depends on 10) The method of claim 10, further comprising: receiving a second indication of a second context switch by the processor, wherein the second context switch is to resume the execution of the first software process; and based on the second indication, recovering the first microarchitectural prediction state information from the repository. ### Claim 12 (depends on 10) The method of claim 10, wherein: the processor is coupled to a random access memory; and a portion of the random access memory comprises the repository. ### Claim 13 (depends on 10) The method of claim 10, wherein the first prediction circuitry comprises one of a conditional branch predictor, an indirect branch predictor, a branch target buffer, or a return predictor. ### Claim 14 (depends on 10) The method of claim 10, wherein automatically saving the version of the first microarchitectural prediction state information comprises encrypting the first microarchitectural prediction state information. ### Claim 15 (depends on 10) The method of claim 10, wherein automatically saving the version of the first microarchitectural prediction state information comprises providing to the repository tag information which identifies the first software process. ### Claim 16 A system comprising: processor comprising: a first execution engine of a first core, the first execution engine to perform an execution of a first software process; first prediction circuitry of the first core, the first prediction circuitry to generate first microarchitectural prediction state information based on the execution; and first prediction state manager circuitry coupled to the first prediction circuitry, the first prediction state manager circuitry to: receive a first indication of a first context switch which is to stop the execution of the first software process with the first core; and automatically save a version of the first microarchitectural prediction state information, based on the first indication, to a repository which is external to the first core; and a main memory coupled to the processor. ### Claim 17 (depends on 16) The system of claim 16, wherein the first prediction state manager circuitry is further to: receive a second indication of a second context switch which is to resume the execution of the first software process; and recover the first microarchitectural prediction state information from the repository based on the second indication. ### Claim 18 (depends on 16) The system of claim 16, wherein the first prediction circuitry comprises one of a conditional branch predictor, an indirect branch predictor, a branch target buffer, or a return predictor. ### Claim 19 (depends on 16) The system of claim 16, the processor further comprising a cryptographic engine to perform an encryption process to generate the version of the first microarchitectural prediction state information. ### Claim 20 (depends on 16) The system of claim 16, wherein the first core further comprises a context tagger circuit to tag the version of the first microarchitectural prediction state information with tag information which identifies the first software process.