On chip dense memory for temporal buffering

An apparatus comprising:

• processor circuitry coupled to a memory associated with cache and processing resources of the processing circuitry, the processing circuitry to facilitate the memory to communicate sets of data with the cache such that the processing resources to seamlessly perform processing of the sets of data during varying time periods.

A method comprising:

• facilitating, by processor circuitry of a computing device, a memory to communicate sets of data with cache such that processing resources associated with the processing circuitry to seamlessly perform processing of the sets of data during varying time periods, wherein the memory is associated with the cache and the processing resources.

At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:

• facilitating a memory to communicate sets of data with cache such that processing resources to seamlessly perform processing of the sets of data during varying time periods, wherein the memory is associated with the cache and the processing resources associated with processing circuitry of the computing device.