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US 2025/0199764 A1Published application
Parallel deterministic stochastic rounding
AssigneeNVIDIA Corporation
InventorsQinglong Chang, Shijiang Yu
Life of this patent
Estimating the term…
Abstract
Disclosed are systems and techniques for parallel deterministic stochastic rounding. In one embodiment, the techniques include obtaining a first set of values of a first bit-length and a second set of values of the first bit-length and generating a third set of values of a second bit-length. Each value of the third set of values is a lower precision value of a corresponding value of the first set of values. The techniques include generating a fourth set of values of the second bit-length, and each value of the fourth set of values is a lower precision value of a corresponding value of the second set of values. Generating the third set of values and the fourth set of values is performed in parallel.
Claims20
A method comprising:
- obtaining a first set of values of a first bit-length and a second set of values of the first bit-length;
- generating a third set of values of a second bit-length, wherein each value of the third set of values is a lower precision value of a corresponding value of the first set of values, wherein the generating the third set of values comprises:
- obtaining a first random value using a first pseudo-random number generator;
- and
- generating a first value based on a comparison of the first random value and the corresponding value of the first set of values;
- and
- generating a fourth set of values of the second bit-length, wherein each value of the fourth set of values is a lower precision value of a corresponding value of the second set of values, wherein the generating the fourth set of values comprises:
- obtaining a second random value using a second pseudo-random number generator;
- and
- generating a second value based on a comparison of the second random value and the corresponding value of the second set of values;
- and
- wherein the generating the third set of values and the generating the fourth set of values is performed in parallel.
9 more elements
A system comprising:
- a memory device;
- and
- one or more circuit groups communicatively coupled to the memory device, the one or more circuit groups to:
- obtain a first set of values of a first bit-length and a second set of values of the first bit-length;
- generate a third set of values of a second bit-length, wherein each value of the third set of values is a lower precision value of a corresponding value of the first set of values, wherein to generate the third set of values the one or more circuit groups are to:
- obtain a first random value using a first pseudo-random number generator;
- and
- generate a first value based on a comparison of the first random value and the corresponding value of the first set of values;
- and
- generate a fourth set of values of the second bit-length, wherein each value of the fourth set of values is a lower precision value of a corresponding value of the second set of values, wherein to generate the fourth set of values the one or more circuit groups are to:
- obtain a second random value using a second pseudo-random number generator;
- and
- generate a second value based on a comparison of the second random value and the corresponding value of the second set of values;
- and
- wherein the one or more circuit groups generate the third set of values and generate the fourth set of values in parallel.
12 more elements
A system comprising:
- a memory device;
- and
- one or more circuit groups communicatively coupled to the memory device, the one or more circuit groups comprising:
- a first circuit group to:
- obtain a first set of values of a first bit-length;
- generate a third set of values of a second bit-length, wherein each value of the third set of values is a lower precision value of a corresponding value of the first set of values, wherein to generate the third set of values the first circuit group is to:
- obtain a first random value using a first pseudo-random number generator;
- and
- generate a first value based on a comparison of the first random value and the corresponding value of the first set of values;
- and
- a second circuit group to:
- obtain a second set of values of the first bit-length;
- generate a fourth set of values of the second bit-length, wherein each value of the fourth set of values is a lower precision value of a corresponding value of the second set of values, wherein to generate the fourth set of values the second circuit group is to:
- obtain a second random value using a second pseudo-random number generator;
- and
- generate a second value based on a comparison of the second random value and the corresponding value of the second set of values;
- and
- wherein the first circuit group and the second circuit group execute in parallel.
15 more elements
Dependencies are inferred from the claim text.