US 2025/0189948 A1 · PIXEL-BASED RULE CHECK FOR LAYOUTS

Abstract

Some embodiments provide a method for performing pixel-based rule checking on a layout that is used in a process for designing or manufacturing an integrated circuit. This pixel-based method provides an optimal approach for performing rule checks for layouts having shapes with curvilinear contours (i.e., with curvilinear edges). This method in some embodiments performs the rule check on a per pixel-basis that is optimal for curvilinear edges on which one or more pixels reside. In some embodiments, the layout is a mask layout used to manufacture the IC, while in other embodiments, the layout is a design layout used to design the IC (e.g., a layout used during the physical design process).

Claims20

Dependent claims

A method for performing rule checks on a set of shapes in a layout used for designing or manufacturing components on a substrate, the method comprising:

assigning a plurality of pixels that are part of the layout to a plurality of processing threads executed by a set of one or more processing units;
using each particular processing thread that is assigned to each particular pixel to perform a rule check with respect to a set of shapes that are within a threshold distance of the particular pixel;
and
after identifying a rule-check violation for the particular pixel, recording in a storage a set of one or more layout locations associated with the identified rule-check violation for subsequent analysis and modification of the layout to resolve the identified rule-check violation.

1 more element

Dependencies are inferred from the claim text.

Pixel-based rule check for layouts

Life of this patent

Pixel-based rule check for layouts

Life of this patent

Abstract

Claims20