Semiconductor package and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyoungok JUNG, Jakyoung GU, Kyungtae KIM, Minsoo KIM, Hyunwoong HAN
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor package includes forming a metal seed layer on a metal pad, coating a photoresist on the metal seed layer and exposing and developing the photoresist to form an opening, performing ion implantation into a surface of the photoresist and a surface of the metal seed layer exposed by the opening, filling the opening with a metal material to form a metal post electrically connected to the metal pad, and removing the photoresist.
Claims20
A method of manufacturing a semiconductor package, the method comprising:
- forming a first wiring structure including a plurality of first wiring patterns and a first insulation layer surrounding the plurality of first wiring patterns, the first wiring structure including a chip mount region and an outer region surrounding the chip mount region, the plurality of first wiring patterns including a plurality of first connection pads;
- coating a photoresist on the first wiring structure and exposing and developing the photoresist to form a plurality of openings on the outer region of the first wiring structure;
- performing ion implantation into a surface of the photoresist and surfaces of the plurality of first connection pads exposed by the plurality of openings;
- filling the plurality of openings with a conductive material to form a plurality of conductive posts connected to the plurality of first connection pads;
- removing the photoresist;
- placing a semiconductor chip on the chip mount region of the first wiring structure;
- forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts;
- and
- forming a second wiring structure on the encapsulant, the second wiring structure including a plurality of second wiring patterns, a plurality of second connection pads electrically connected to the plurality of conductive posts, and a second insulation layer surrounding the plurality of second wiring patterns.
A method of manufacturing a semiconductor package, the method comprising:
- forming a metal seed layer on a metal pad;
- coating a photoresist on the metal seed layer and exposing and developing the photoresist to form an opening;
- performing ion implantation into a surface of the photoresist and a surface of the metal seed layer exposed by the opening;
- filling the opening with a metal material to form a metal post electrically connected to the metal pad;
- and
- removing the photoresist.
A method of manufacturing a semiconductor package, the method comprising:
- preparing a supporting substrate;
- forming a first wiring structure on the supporting substrate, the first wiring structure including a first chip mount region and a first outer region surrounding the first chip mount region;
- coating a photoresist on the first wiring structure and exposing and developing the photoresist to form a plurality of openings on the first outer region of the first wiring structure;
- performing ion implantation into an upper surface and a sidewall of the photoresist and an upper surface of the first wiring structure exposed by the plurality of openings;
- performing rinsing treatment and acid treatment on the supporting substrate;
- filling the plurality of openings with a conductive material to form a plurality of conductive posts;
- removing the photoresist;
- placing a first semiconductor chip on the first chip mount region of the first wiring structure;
- forming an encapsulant surrounding the first semiconductor chip and the plurality of conductive posts;
- forming a second wiring structure on the encapsulant, the second wiring structure including a second chip mount region and a second outer region surrounding the second chip mount region;
- and
- placing a second semiconductor chip on the second chip mount region of the second wiring structure.
Dependencies are inferred from the claim text.