# US 2025/0169166 A1 · Enhanced isolation for on-chip current sensors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0169166 A1 - Document ID: US20250169166A1 - Status: Published application - Kind: A1 - Application number: 18/510,756 - Filed: 2023-11-16 - Published: 2025-05-22 - Earliest claimed: 2023-11-16 - Assignees: Wolfspeed, Inc. - Applicants: Wolfspeed, Inc. - Inventors: Madankumar Sampath; Sei-Hyung Ryu - Web page: https://patentgrep.com/patent/US20250169166A1 ## CPC - H10D 84/83: of only insulated-gate FETs [IGFET] - H10W 10/031: {of isolation regions comprising PN junctions} - G01R 19/0046: {characterised by a specific application or detail not covered by any other subgroup of G01R19/00} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 30/669: {having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0156: {Manufacturing their doped wells} - H10D 84/141: {VDMOS having built-in components} - H10W 10/30: Isolation regions comprising PN junctions - H10D 8/50: PIN diodes - H10D 8/60: Schottky-barrier diodes - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A semiconductor device includes a device active region comprising a first well, at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET), and a sensor region comprising a second well, at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET. A distance between an outer edge of the second well and an inner edge of the first well is constant or the distance decreases approaching one or more vertices of the second well. ## Claims ### Claim 1 A semiconductor device, comprising: a device active region comprising a first well, at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET); and a sensor region comprising a second well, at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET, wherein a distance between an outer edge of the second well and an inner edge of the first well is constant or the distance decreases approaching one or more vertices of the second well. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising an isolation structure between the first and second wells. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein each of the first and second wells comprises material of a second conductivity type, and wherein the isolation structure comprises material of a first conductivity type, the first conductivity type being opposite in polarity to the second conductivity type. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the isolation structure is configured to electrically isolate the first and second wells. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein the isolation structure further comprises material of the second conductivity type that is located in at least one corner region of the isolation structure so that the isolation structure is configured to provide a high-resistance electrical connection between the first and second wells. ### Claim 6 (depends on 2) The semiconductor device according to claim 2, wherein the isolation structure is configured to provide a high-resistance electrical connection between the first and second wells. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein each of the first and second wells comprises a first material and at least one corner of the isolation structure comprises a second material that is different from the first material. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the second material comprises silicon or nickel oxide and the first material comprises silicon carbide. ### Claim 9 (depends on 2) The semiconductor device according to claim 2, wherein each of the second well and the isolation structure are circular in shape and concentric with each other when viewed in plan view. ### Claim 10 (depends on 2) The semiconductor device according to claim 2, wherein each of the second well and the isolation structure are rectangular in shape and have rounded corners when viewed in plan view. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein a distance, in plan view, across the isolation structure between the first and second wells is constant. ### Claim 12 (depends on 3) The semiconductor device according to claim 3, wherein the isolation structure further comprises material having the second conductivity type adjacent at least one of the corners of the second well. ### Claim 13 (depends on 2) The semiconductor device according to claim 2, wherein a shape defined by the outer edge of the second well is different than a shape defined by the inner edge of the first well. ### Claim 14 (depends on 2) The semiconductor device according to claim 2, wherein the isolation structure comprises a trench that is at least partially filled with an insulating material. ### Claim 15 (depends on 3) The semiconductor device according to claim 3, wherein the isolation structure further comprises wedge-shaped regions comprising material of the second conductivity type at corners thereof, each of the wedge-shaped regions extending outwardly from the second well to the first well and forming a point connection with the first well for providing a high-resistance electrical connection between the first and second wells. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein each of the first and/or second MOSFET comprises a plurality of unit cells. ### Claim 17 A semiconductor device, comprising: a device active region comprising a first well, at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET); and a sensor active region comprising a second well, at least a portion of the second well being part of a second MOSFET that is configured to mirror a current in the first MOSFET, wherein, when viewed in plan view, the first well surrounds the second well and a distance between an outer edge of the second well and an inner edge of the first well at corners of the second well is less than or equal to the distance between the outer edge of the second well and the inner edge of the first well at sides of the second well. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the outer edge of the second well and the inner edge of the first well at one or more corners of the second well are rounded, such that a distance, in a plan view, between the first and second wells is constant. ### Claim at position 19 -30. (canceled) ### Claim 31 (depends on 17) The semiconductor device according to claim 17, wherein, when viewed in plan view, an area defined by an outer edge of the second well and an inner edge of the first well is configured having wedge-shaped implanted regions at corners thereof, each of the wedge-shaped implanted regions extending between the second well to the first well and forming a point connection with one of the first well and the second well for providing a high-resistance electrical connection between the first and second wells. ### Claim at position 21 -40. (canceled) ### Claim 41 A method of forming a semiconductor device comprising an on-chip current mirror, the method comprising: providing a device active region comprising a first well, at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET); providing a sensor active region comprising a second well, at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET; and providing an isolation structure between the first and second wells, wherein a distance between outer edges of the second well and inner edges of the first well is constant or the distance decreases approaching one or more vertices of the second well. ### Claim at position 23 -55. (canceled) ### Claim 56 A method of forming a semiconductor device comprising an on-chip current mirror, the method comprising: providing a device active region comprising a first well, the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET); and providing a sensor active region comprising a second well, the second well being part of a second MOSFET that is configured to mirror a current in the first MOSFET; wherein the second well is laterally separated from the first well, a distance between an outer edge of the second well and an inner edge of the first well at corners of the second well being less than or equal to the distance between the outer edge of the second well and the inner edge of the first well at sides of the second well. ### Claim at position 25 -61. (canceled)