# US 2025/0169104 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0169104 A1 - Document ID: US20250169104A1 - Status: Published application - Kind: A1 - Application number: 19/033,307 - Filed: 2025-01-21 - Published: 2025-05-22 - Earliest claimed: 2021-09-22 - Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Inventors: Takahiro OGATA; Teruyuki OHASHI; Hiroshi KONO - Web page: https://patentgrep.com/patent/US20250169104A1 ## CPC - H10D 30/665: {having edge termination structures} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 62/8325: {Silicon carbide} - H10D 84/143: {the built-in components being PN junction diodes} - H10D 84/146: {the built-in components being Schottky barrier diodes} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/837: {comprising vertical IGFETs} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device of embodiments includes: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The termination region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes the silicon carbide layer. The width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice the thickness of the silicon carbide layer. ## Claims ### Claim 1 A semiconductor device, comprising: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion, wherein the element region includes: a first electrode; a second electrode; a gate electrode; a silicon carbide layer provided between the first electrode and the second electrode, having a first face on a side of the first electrode and a second face on a side of the second electrode, and including: a first silicon carbide region of a first conductive type having a first region and a second region, the first region being in contact with the first face and facing the gate electrode, and the second region being in contact with the first face and in contact with the first electrode; a second silicon carbide region of a second conductive type provided between the first silicon carbide region and the first face, the second silicon carbide region being adjacent to the first region, the second silicon carbide region facing the gate electrode, and the second silicon carbide region being in contact with the first electrode at a first interface; and a third silicon carbide region of a first conductive type provided between the second silicon carbide region and the first face and electrically connected to the first electrode; and a gate insulating layer provided between the gate electrode and the second silicon carbide region and between the gate electrode and the first region, the termination region includes: a first wiring layer electrically connected to the first electrode; the second electrode; and the silicon carbide layer including the first silicon carbide region and a fourth silicon carbide region of a second conductive type, the fourth silicon carbide region provided between the first silicon carbide region and the first face, the fourth silicon carbide region being in contact with the first wiring layer at a second interface, the intermediate region includes the silicon carbide layer including the first silicon carbide region and a fifth silicon carbide region of a second conductive type, the fifth silicon carbide region provided between the first silicon carbide region and the first face, the transistor includes the gate electrode, the gate insulating layer, the first region, the second silicon carbide region, and the third silicon carbide region, the first diode includes the first electrode and the second region, the first contact portion includes the first interface, the second contact portion includes the second interface, and a width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice a thickness of the silicon carbide layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the intermediate region further includes a connection layer connecting the first electrode and the first wiring layer to each other, and the connection layer is not in contact with the fifth silicon carbide region. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the gate electrode extends in a first direction parallel to the first face. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the connection layer is provided in a second direction of the first electrode, and the second direction is parallel to the first face and perpendicular to the first direction. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the first wiring layer has a first portion extending in the second direction, a second portion extending in the second direction, a third portion extending in the first direction, and a fourth portion extending in the first direction, the first electrode is interposed between the first portion and the second portion and between the third portion and the fourth portion, and the connection layer is provided between the first electrode and the fourth portion. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the intermediate region further includes a gate electrode pad and a second wiring layer electrically connected to the gate electrode pad, the gate electrode is electrically connected to the gate electrode pad through the second wiring layer, and the second wiring layer has a first line extending in the second direction and provided between the first portion and the first electrode and a second line extending in the second direction and provided between the second portion and the first electrode. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the first electrode, the first wiring layer, the connection layer, the gate electrode pad, and the second wiring layer contain a same material. ### Claim 8 (depends on 3) The semiconductor device according to claim 3, wherein a first width of the intermediate region in a second direction perpendicular to the first direction is larger than a second width of the intermediate region in the first direction. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the termination region includes a second diode, the first silicon carbide region included in the termination region has a third region in contact with the first face and in contact with the first wiring layer, and the second diode includes the first wiring layer and the third region. ### Claim 10 A semiconductor device, comprising: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion, wherein the element region includes: a first electrode; a second electrode; a gate electrode; a silicon carbide layer provided between the first electrode and the second electrode, having a first face on a side of the first electrode and a second face on a side of the second electrode, and including: a first silicon carbide region of a first conductive type having a first region and a second region, the first region being in contact with the first face and facing the gate electrode and the second region being in contact with the first face and in contact with the first electrode; a second silicon carbide region of a second conductive type provided between the first silicon carbide region and the first face, the second silicon carbide region being adjacent to the first region, the second silicon carbide region facing the gate electrode, and the second silicon carbide region being in contact with the first electrode at a first interface; and a third silicon carbide region of a first conductive type provided between the second silicon carbide region and the first face and electrically connected to the first electrode; and a gate insulating layer provided between the gate electrode and the second silicon carbide region and between the gate electrode and the first region, the termination region includes: the first electrode; the second electrode; and the silicon carbide layer including the first silicon carbide region and a fourth silicon carbide region of a second conductive type, the fourth silicon carbide region provided between the first silicon carbide region and the first face, the fourth silicon carbide region being in contact with the first electrode at a second interface, the intermediate region includes: the first electrode; the second electrode; and the silicon carbide layer including the first silicon carbide region and a fifth silicon carbide region of a second conductive type, the fifth silicon carbide region provided between the first silicon carbide region and the first face, the transistor includes the gate electrode, the gate insulating layer, the first region, the second silicon carbide region, and the third silicon carbide region, the first diode includes the first electrode and the second region, the first contact portion includes the first interface, the second contact portion includes the second interface, and a width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice a thickness of the silicon carbide layer. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the termination region includes a second diode, the first silicon carbide region included in the termination region has a third region in contact with the first face and in contact with the first electrode, and the second diode includes the first electrode and the third region. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein the intermediate region further includes: a gate electrode pad; and a gate wiring layer provided between the first electrode and the silicon carbide layer, the gate wiring layer electrically connected to the gate electrode pad and the gate electrode, and the gate wiring layer including a first gate line extending in a second direction perpendicular to a first direction parallel to the first face and a second gate line extending in the second 10 direction, the gate electrode being interposed between the first gate line and the second gate line.