# US 2025/0169079 A1 · Method for forming a semiconductor structure

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- Number: US 2025/0169079 A1
- Document ID: US20250169079A1
- Status: Published application
- Kind: A1
- Application number: 18/404,839
- Filed: 2024-01-04
- Published: 2025-05-22
- Earliest claimed: 2023-11-16
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Fu-Shou Tsai; Chau-Chung Hou; Yong-Yi Lin; Yang-Ju Lu; Yu-Lung Shih; Ren-Peng Huang; Ching-Yang Chuang
- Web page: https://patentgrep.com/patent/US20250169079A1

## CPC

- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
providing a substrate having a memory array region and a peripheral region thereon;
forming a memory structure on the substrate within the memory array region, wherein a step height is formed between the memory array region and the peripheral region;
blanketly depositing a dielectric layer over the memory array region and the peripheral region, wherein the dielectric layer covers the memory structure;
performing a reverse etching process to remove a portion of the dielectric layer from a central area of the memory array region, thereby forming an upwardly protruding wall structure along a perimeter of the memory array region, wherein a remaining thickness of the dielectric layer within the central area of the memory array region is equal to a combination of a polishing buffer thickness and a target thickness;
subjecting the dielectric layer to a first polishing process to remove the upwardly protruding wall structure from the memory array region; and
subjecting the dielectric layer to a second polishing process to remove an upper portion of the dielectric layer having the polishing buffer thickness from the memory array region, wherein a remainder of the dielectric layer within the memory array region has the target thickness above the memory structure.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the dielectric layer comprises a low-k or ultra-low k dielectric material layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the dielectric layer has a thickness of 1500 to 2500 angstroms.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the remaining thickness of the dielectric layer within the central area of the memory array region is 500-600 angstroms.

### Claim 5 (depends on 3)

The method according to claim 3, wherein the remaining thickness of the dielectric layer within the central area of the memory array region is 550 angstroms.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the polishing buffer thickness is 250 to 350 angstroms.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the target thickness is 200 to 300 angstroms.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the memory structure comprises a conductive via embedded in a first intermediate dielectric layer, a memory storage structure embedded in a second intermediate dielectric layer, and a protective layer covering a sidewall of the memory storage structure and the first intermediate dielectric layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the memory storage structure comprises a magnetic tunneling junction (MTJ) structure situated directly on the conductive via.

### Claim 10 (depends on 8)

The method according to claim 8, wherein the conductive via comprises a tungsten via.

### Claim 11 (depends on 8)

The method according to claim 8, wherein the first intermediate dielectric layer extends onto the peripheral region.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the dielectric layer is in direct contact with the first intermediate dielectric layer within the peripheral region.

### Claim 13 (depends on 1)

The method according to claim 1, wherein the dielectric layer has a thickness T and the upwardly protruding wall structure has a height H, and wherein a ratio of the height H to the thickness T is between ½ and ¾.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the remaining thickness of the dielectric layer within the central area of the memory array region ranges between ½ and ¼ of the thickness T of the dielectric layer.

### Claim 15 (depends on 13)

The method according to claim 13, wherein the remaining thickness of the dielectric layer within the central area of the memory array region is ⅓ of the thickness T of the dielectric layer.