# US 2025/0168520 A1 · Integrated circuit with multi-application image processing

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- Number: US 2025/0168520 A1
- Document ID: US20250168520A1
- Status: Published application
- Kind: A1
- Application number: 19/027,193
- Filed: 2025-01-17
- Published: 2025-05-22
- Earliest claimed: 2022-05-26
- Applicants: Texas Instruments Incorporated
- Inventors: Niraj Nandan; Mihir Mody; Rajasekhar Allu; Manoj Koul; Pandy Kalimuthu; David Stoller
- Web page: https://patentgrep.com/patent/US20250168520A1

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- H04N 23/81: for suppressing or minimising disturbance in the image signal generation
- G06T 3/4015: Image demosaicing, e.g. colour filter arrays [CFA] or Bayer patterns
- H04N 23/843: {Demosaicing, e.g. interpolating colour pixel values}
- H04N 23/88: for colour balance, e.g. white-balance circuits or colour temperature control
- H04N 5/21: Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
- H04N 23/80: Camera processing pipelines; Components thereof
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

## Claims

### Claim 1

A device comprising:
a first processing pipeline that includes:
first processing circuitry configured to perform a first operation on a set of data; and
second processing circuitry coupled to the first processing circuitry and configured to perform a second operation on the set of data;
a second processing pipeline that includes:
the first processing circuitry;
third processing circuitry coupled to the first processing circuitry and configured to perform a third operation on the set of data; and
a memory circuit coupled between the first processing circuitry and the third processing circuitry.

### Claim 2 (depends on 1)

The device of claim 1, wherein the memory circuit is configured to provide a configurable delay to synchronize output data of the second processing circuitry and output data of the third processing circuitry.

### Claim 3 (depends on 1)

The device of claim 1, wherein the memory circuit is configured to synchronize output data of the second processing circuitry and output data of the third processing circuitry such that a difference between a horizontal delay of the output data of the second processing circuitry and a horizontal delay of the output data of the third processing circuitry is less than or equal to a horizontal blanking period.

### Claim 4 (depends on 1)

The device of claim 1, wherein:
the first processing pipeline includes fourth processing circuitry coupled between the first processing circuitry and the second processing circuitry; and
the second processing pipeline includes a multiplexer that includes:
a first input coupled to an output of the first processing circuitry;
a second input coupled to an output of the fourth processing circuitry; and
an output coupled to the memory circuit.

### Claim 5 (depends on 4)

The device of claim 4, wherein the memory circuit is configured to provide an amount of delay that is based on whether the multiplexer is controlled to couple the output of the first processing circuitry to the memory circuit or to couple the output of the fourth processing circuitry to the memory circuit.

### Claim 6 (depends on 1)

The device of claim 1 further comprising:
a buffer coupled to the second processing circuitry and the third processing circuitry; and
a set of processing circuitry blocks coupled to the buffer, wherein the buffer is configured to:
provide output data of the second processing circuitry to any of the set of processing circuitry blocks; and
provide output data of the third processing circuitry to any of the set of processing circuitry blocks.

### Claim 7 (depends on 1)

The device of claim 1, wherein the set of processing circuitry blocks includes at least one of: a lens distortion correction circuit, a noise filter circuit, a multi-scalar circuit, or a direct memory access circuit.

### Claim 8 (depends on 1)

The device of claim 1, wherein the first processing circuitry is configured to couple to an image capture device to receive the set of data from the image capture device.

### Claim 9

A device comprising:
first processing circuitry that includes:
an input; and
an output;
second processing circuitry that includes:
an input coupled to the output of the first processing circuitry; and
an output;
a memory that includes:
an input coupled to the output of the first processing circuitry; and
an output;
third processing circuitry that includes:
an input coupled to the output of the memory; and
an output.

### Claim 10 (depends on 9)

The device of claim 9, wherein the memory is configured to provide a configurable delay such that output data of the second processing circuitry is synchronized to output data of the third processing circuitry.

### Claim 11 (depends on 9)

The device of claim 9, wherein the memory is configured to synchronize output data of the second processing circuitry and output data of the third processing circuitry such that a difference between a horizontal delay of the output data of the second processing circuitry and a horizontal delay of the output data of the third processing circuitry is less than or equal to a horizontal blanking period.

### Claim 12

A device comprising:
an interface configured to couple to an image capture device;
a set of image processing circuitry blocks that includes:
a first image processing circuitry block that includes:
a first processing stage that includes:
an input; and
an output;
a second processing stage that includes:
an input; and
an output;
a set of intermediate processing stages coupled between the output of the first processing stage and the input of the second processing stage;
a multiplexer that includes:
a first input coupled to the output of the first processing stage;
a second input coupled to an output of the set of intermediate processing stages; and
an output;
a first memory circuit that includes:
an input coupled to the output of the multiplexer; and
an output; and
a third processing stage that includes:
an input coupled to the output of the first memory circuit; and
an output; and
a second memory circuit coupled to each of the set of image processing circuitry blocks, wherein the second memory circuit is coupled to the output of the second processing stage and the output of the third processing stage.

### Claim 13 (depends on 12)

The device of claim 12, wherein the first memory circuit is configured to provide a configurable delay to synchronize output data of the second processing stage and output data of the third processing stage.

### Claim 14 (depends on 12)

The device of claim 12, wherein the first memory circuit is configured to synchronize output data of the second processing stage and output data of the third processing stage such that a difference between a horizontal delay of the output data of the second processing stage and a horizontal delay of the output data of the third processing stage is less than or equal to a horizontal blanking period.

### Claim 15 (depends on 12)

The device of claim 12, wherein the first memory circuit is configured to provide an amount of delay that is based on whether the multiplexer is controlled to couple the output of the first processing stage to the memory circuit or to couple the output of the set of intermediate processing stages to the first memory circuit.

### Claim 16 (depends on 12)

The device of claim 12, wherein the set of image processing circuitry blocks includes at least one of: a lens distortion correction circuit, a noise filter circuit, a multi-scalar circuit, or a direct memory access circuit.

### Claim 17 (depends on 12)

The device of claim 12, wherein:
the interface is configured to receive a set of data from the image capture device; and
the first processing stage is configured to perform at least one of: wide dynamic range merge, defect pixel correction, lens shading correction, decompounding, auto-focus, auto-exposure, auto-white balance, or white balance on the set of data.

### Claim 18 (depends on 12)

The device of claim 12, wherein:
the interface is configured to receive a set of data from the image capture device;
the second processing stage is configured to provide a first set of output data based on the set of data, wherein the first set of data is in a first color space; and
the third processing stage is configured to provide a second set of output data based on the set of data, wherein the first set of data is in a second color space that is different from the first color space.

### Claim 19 (depends on 18)

The device of claim 18, wherein:
the first color space is a YUV8 color space; and
the second color space is a Y12UV8 color space.

### Claim 20 (depends on 12)

The device of claim 12, wherein:
the interface is configured to receive a set of data from the image capture device;
the second processing stage is configured to provide a first set of output data based on the set of data, wherein the first set of data has a first number of color channels; and
the third processing stage is configured to provide a second set of output data based on the set of data, wherein the first set of data has a second number of color channels that is different from the first number of color channels.