# US 2025/0167792 A1 · Dithering based digital to time converter linearization technique

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- Number: US 2025/0167792 A1
- Document ID: US20250167792A1
- Status: Published application
- Kind: A1
- Application number: 18/887,955
- Filed: 2024-09-17
- Published: 2025-05-22
- Earliest claimed: 2023-11-17
- Assignees: University of Southern California
- Applicants: University of Southern California
- Inventors: Shuo-Wei Chen; Qiaochu Zhang
- Web page: https://patentgrep.com/patent/US20250167792A1

## CPC

- H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)}
- H03L 7/08: Details of the phase-locked loop
- H03L 2207/50: All digital phase-locked loop
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

An electrical circuit for clock generation includes a digital-to-time converter error scrambler configured to randomize error in a digital-to-time converter (DTC) and configured to suppress spurs of the electrical circuit, a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into the DTC at a first point and an injection of the reference signal into the DTC as a second point, and a background delay equalizer configured to calibrate errors of the electrical circuit.

## Claims

### Claim 1

An electrical circuit for clock generation comprising:
a digital-to-time converter error scrambler configured to randomize error in a digital-to-time converter (DTC) and configured to suppress spurs of the electrical circuit;
a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into an oscillator at a first point and an injection of the reference signal into the oscillator at a second point; and
a background delay equalizer configured to calibrate errors of the electrical circuit.

### Claim 2 (depends on 1)

The electrical circuit of claim 1, wherein randomization from the digital-to-time converter error scrambler and calibration from the background delay equalizer occur simultaneously.

### Claim 3 (depends on 1)

The electrical circuit of claim 1, wherein randomization from the digital-to-time converter error scrambler and calibration from the background delay equalizer occur independently.

### Claim 4 (depends on 1)

The electrical circuit of claim 1, wherein the errors calibrated by the background delay equalizer are any one of a digital-to-time converter offset, a digital-to-time converter gain, or an integral-nonlinearity (INL) error.

### Claim 5 (depends on 3)

The electrical circuit of claim 3, wherein the errors exist at at least one point of a phase-locked loop.

### Claim 6 (depends on 1)

The electrical circuit of claim 1, wherein a timing mismatch is associated with the digital-to-time converter error scrambler.

### Claim 7 (depends on 1)

The electrical circuit of claim 1, wherein the electrical circuit is further configured to include one or more of a pulse window generator, an injection path, a digital-controlled oscillator, an injection mixer, an injection digital-to-time converter, or a calibration digital-to-time converter.

### Claim 8 (depends on 1)

The electrical circuit of claim 1, wherein outputs of the background error compensator and the background delay equalizer are combined digitally before adjusting a delay of a calibration digital-to-time converter.

### Claim 9 (depends on 7)

The electrical circuit of claim 7, wherein the pulse window generator controls the timing of a reference injection and an injection polarity.

### Claim 10

An electrical circuit for clock generation comprising:
an oscillator;
a digital-to-time converter (DTC) error scrambler configured to randomize error in a DTC and configured to suppress spurs of the electrical circuit, wherein the DTC error scrambler comprises control code to control a delay of one or more injection DTCs;
a background error compensator configured to mitigate a timing mismatch between an injection of a reference signal into the oscillator at a first point and an injection of the reference signal into the oscillator at a second point; and
a background delay equalizer configured to calibrate errors of the electrical circuit, wherein the errors comprise a plurality of error components.

### Claim 11 (depends on 10)

The electrical circuit of claim 10, wherein the background delay equalizer comprises:
digital domain corrector configured to tune the oscillator to align with a phase of at least one of the injection DTCs to control a first error component of the plurality of error components;
a current source configured to control a second error component of the plurality of error components; and
a calibration DTC configured to control a third error component of the plurality of error components.

### Claim 12 (depends on 11)

The electrical circuit of claim 11, wherein the first error component is a digital-to-time converter offset error, the second error component is a digital-to-time converter gain error, and the third error component is a digital-to-time converter integral-nonlinearity (INL) error.

### Claim 13 (depends on 12)

The electrical circuit of claim 12, wherein the calibration DTC controls the third error component by reducing a delay range relative to a delay range of an injection DTC.

### Claim 14 (depends on 11)

The electrical circuit of claim 11, wherein mitigating the timing mismatch between the injection of the reference signal into the oscillator at the first point and the injection of the reference signal into the oscillator at the second point comprises:
extracting, by the background error compensator, using a filter, the timing mismatch between the injection of the reference signal at the first point and the injection of the reference signal at the second point; and
tuning control code of the calibration DTC to calibrate a time delay of one or both of the injection of the reference signal at the first point and the injection of the reference signal at the second point.

### Claim 15 (depends on 10)

The electrical circuit of claim 10, the electrical circuit further comprising a reference signal configured to periodically refresh a signal of the oscillator to suppress noise in the oscillator, wherein the reference signal is a low noise signal.

### Claim 16 (depends on 10)

The electrical circuit of claim 10, wherein a total delay of the one or more injection DTCs is determined based on a product of a gain of the injection DTC and the control code of the injection DTC.

### Claim 17 (depends on 10)

The electrical circuit of claim 10, wherein the background delay equalizer comprises a least mean square filter.

### Claim 18

A method comprising:
controlling, using a digital-to-time converter (DTC) error scrambler, a delay of one or more injection DTCs of an electrical circuit;
mitigating, using a background error compensator, a timing mismatch between an injection of a reference signal into an oscillator at a first point and an injection of the reference signal into the oscillator at a second point; and
calibrating, using a delay equalizer, error of the electrical circuit, the error comprising a plurality of error components.

### Claim 19 (depends on 18)

The method of claim 18, wherein calibrating the plurality of error components comprises:
tuning a signal of the oscillator to align with a phase of at least one of the one or more injection DTCs to control a first error component of the plurality of error components;
controlling a current source to correct a gain of the injection DTC; and
tuning a delay range relative to a delay range of an injection DTC via a calibration DTC.

### Claim 20 (depends on 18)

The method of claim 18, wherein mitigating the timing mismatch comprises:
extracting, by the background error compensator, using a filter, the timing mismatch between the injection of the reference signal at the first point and the injection of the reference signal at the second point; and
tuning control code of the calibration DTC to calibrate a time delay of one or both of the injection of the reference signal at the first point and the injection of the reference signal at the second point.