Power amplifier equalizer

A differential amplifier, including:

• (a) a first main field-effect transistor (FET) including a first gate coupled to a first bias voltage;
• (b) a second main FET including a second gate coupled to a second bias voltage;
• and
• (c) an equalization circuit including:
• (1) one or more first transistors coupled between the second main FET and the first gate of the first main FET;
• and
• (2) one or more second transistors coupled between the first main FET and the second gate of the second main FET;
• wherein the equalization circuit alters the second bias voltage coupled to the second gate of the second main FET in proportion to a first power level present at the first main FET, and alters the first bias voltage coupled to the first gate of the first main FET in proportion to a second power level present at the second main FET.

A differential amplifier, including:

• (a) a first main field-effect transistor (FET) including a gate configured to receive a first input signal, a drain providing a first amplified output signal, and a source coupled to circuit ground;
• (b) a second main FET including a gate configured to receive a second input signal, a drain providing a second amplified output signal, and a source coupled to circuit ground;
• and
• (c) an equalization circuit coupled to the respective gates and drains of the first and second main FETs and configured to generate an equalization voltage that alters a bias voltage to the gates of the respective first and second main FETs in proportion to a power level present at the respective drains of the second and first main FETs, wherein the equalization circuit includes:
• (1) a first subcircuit including one or more transistors, at least one of the one or more transistors of the first subcircuit having a source coupled to the gate of the first main FET and at least one of the one or more transistors of the first subcircuit having a drain coupled to the drain of the second main FET;
• and
• (2) a second subcircuit one or more transistors, at least one of the one or more transistors of the second subcircuit having a first transistor having a source coupled to the gate of the second main FET and at least one of the one or more transistors of the second subcircuit having a drain coupled to the drain of the first main FET.