# US 2025/0167162 A1 · Electronic package and substrate structure thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2025/0167162 A1
- Document ID: US20250167162A1
- Status: Published application
- Kind: A1
- Application number: 18/949,476
- Filed: 2024-11-15
- Published: 2025-05-22
- Earliest claimed: 2023-11-16
- Assignees: Siliconware Precision Industries Co., Ltd.
- Applicants: Siliconware Precision Industries Co., Ltd.
- Inventors: Wei-Hsin SHIH; Chin-Wei HSU; Jui-Kun WANG; Yi-Han LU; Hsiu-Fang CHIEN
- Web page: https://patentgrep.com/patent/US20250167162A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/387: {Flow barriers}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic package and a substrate structure thereof are provided, in which an electronic element is disposed on the substrate structure having a circuit layer, and an insulating protective layer of the substrate structure has an opening that exposes the circuit layer. A plurality of extension portions protruding toward the inside of the opening and spaced apart are formed on the edge of the opening of the insulating protective layer, so that when an underfill material is filled into a space between the electronic element and the substrate structure, the space between the electronic element and the substrate structure can be evenly filled up to prevent the underfill material from forming voids.

## Claims

### Claim 1

A substrate structure, comprising:
a substrate body having a circuit layer and defined with at least one die placement region; and
an insulating protective layer formed on the substrate body and formed with an opening corresponding to the die placement region and exposing the circuit layer, wherein the insulating protective layer is formed with a plurality of spaced extension portions protruding toward an inside of the opening at an edge of the opening.

### Claim 2 (depends on 1)

The substrate structure of claim 1, wherein a length of each of the extension portions is 1200 microns to 1800 microns, and a distance between the extension portions is 70 microns to 130 microns.

### Claim 3 (depends on 1)

The substrate structure of claim 1, wherein the circuit layer has a plurality of conductive traces and a plurality of electrical contact pads connected to the plurality of conductive traces, and the plurality of electrical contact pads are exposed from the single opening.

### Claim 4 (depends on 1)

The substrate structure of claim 1, wherein a plurality of guide blocks arranged and spaced apart are formed in the opening to form a plurality of channels.

### Claim 5 (depends on 1)

The substrate structure of claim 1, wherein the insulating protective layer is formed with at least one recess on a periphery of the die placement region.

### Claim 6 (depends on 5)

The substrate structure of claim 5, wherein the recess communicates with the opening.

### Claim 7 (depends on 1)

An electronic package, comprising:
the substrate structure of claim 1;
an electronic element disposed on the die placement region and electrically connected to the circuit layer; and
an underfill material formed between the substrate structure and the electronic element and filling up the opening.

### Claim 8 (depends on 7)

The electronic package of claim 7, wherein a length of each of the extension portions is 1200 microns to 1800 microns, and a distance between the extension portions is 70 microns to 130 microns.

### Claim 9 (depends on 7)

The electronic package of claim 7, wherein the circuit layer has a plurality of conductive traces and a plurality of electrical contact pads connected to the plurality of conductive traces, and the plurality of electrical contact pads are exposed from the single opening.

### Claim 10 (depends on 9)

The electronic package of claim 9, wherein the electronic element is bonded and electrically connected to the plurality of electrical contact pads via a plurality of conductive bumps.

### Claim 11 (depends on 7)

The electronic package of claim 7, wherein a plurality of guide blocks arranged and spaced apart are formed in the opening to form a plurality of channels.

### Claim 12 (depends on 11)

The electronic package of claim 11, wherein an opening direction of the channel is the same as a molding flow direction of the underfill material.

### Claim 13 (depends on 7)

The electronic package of claim 7, wherein the insulating protective layer is formed with at least one recess on a periphery of the die placement region.

### Claim 14 (depends on 13)

The electronic package of claim 13, wherein the recess communicates with the opening.

### Claim 15 (depends on 7)

The electronic package of claim 7, wherein the electronic element is bonded and electrically connected to the circuit layer via a plurality of conductive bumps.

### Claim 16 (depends on 15)

The electronic package of claim 15, wherein the underfill material covers the plurality of conductive bumps.