# US 2025/0167151 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0167151 A1 - Document ID: US20250167151A1 - Status: Published application - Kind: A1 - Application number: 18/679,992 - Filed: 2024-05-31 - Published: 2025-05-22 - Earliest claimed: 2023-11-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chonghee LEE; Yunrae CHO - Web page: https://patentgrep.com/patent/US20250167151A1 ## CPC - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/30: Die-attach connectors - H10W 72/851: {Dispositions of multiple connectors or interconnections} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a wiring board including a wiring pattern, a solder resist layer on a top surface of the wiring board and defining an opening that exposes the wiring pattern, solder resist patterns arranged in the opening, and a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board. The solder resist patterns are arranged under a first edge of one side of the semiconductor chip. ## Claims ### Claim 1 A semiconductor package comprising: a wiring board including a wiring pattern; a solder resist layer on a top surface of the wiring board, the solder resist layer defining an opening that exposes the wiring pattern; solder resist patterns arranged in the opening; and a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board, wherein the solder resist patterns are arranged under a first edge of one side of the semiconductor chip. ### Claim 2 (depends on 1) The semiconductor package of claim 1, further comprising a plurality of signal bumps between the wiring board and the semiconductor chip, and the plurality of signal bumps connecting the wiring pattern to the semiconductor chip, wherein the plurality of signal bumps are arranged under a center of the semiconductor chip. ### Claim 3 (depends on 2) The semiconductor package of claim 2, further comprising a plurality of dummy bumps that are not electrically connected to the wiring board between the wiring board and the semiconductor chip. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein a size of each of the solder resist patterns is greater than a size of each of the plurality of signal bumps. ### Claim 5 (depends on 2) The semiconductor package of claim 2, wherein the plurality of signal bumps are arranged along a line in a first horizontal direction. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the solder resist patterns are not arranged under a second edge of the semiconductor chip facing the first edge of the semiconductor chip. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip further comprises a second edge extending in a direction intersecting with the first edge, and wherein the solder resist patterns further comprise a portion arranged under the second edge. ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising a molding layer filling a space between the wiring board and the semiconductor chip in the opening. ### Claim 9 A semiconductor package comprising: a wiring board; a semiconductor chip on a top surface of the wiring board and electrically connected to the wiring board; a molding layer between the wiring board and the semiconductor chip and molding the wiring board and the semiconductor chip; and solder resist patterns surrounded by the molding layer under the semiconductor chip, wherein the solder resist patterns are arranged under one side of the semiconductor chip. ### Claim 10 (depends on 9) The semiconductor package of claim 9, further comprising a plurality of signal bumps surrounded by the molding layer between the wiring board and the semiconductor chip, the plurality of signal bumps electrically connecting the wiring board and the semiconductor chip. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the plurality of signal bumps are arranged in a line under a center of the semiconductor chip along a first horizontal direction. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the solder resist patterns are arranged in a line along the first horizontal direction under a first edge of the semiconductor chip extending in the first horizontal direction. ### Claim 13 (depends on 10) The semiconductor package of claim 10, wherein the solder resist patterns are arranged on one side of the plurality of signal bumps and are not arranged on an other side. ### Claim 14 (depends on 10) The semiconductor package of claim 10, wherein the molding layer comprises one or more voids arranged between the plurality of signal bumps and the solder resist patterns. ### Claim 15 (depends on 9) The semiconductor package of claim 9, further comprising a plurality of dummy bumps that are not electrically connected to the wiring board, wherein the solder resist patterns do not overlap the plurality of dummy bumps in a vertical direction. ### Claim 16 (depends on 9) The semiconductor package of claim 9, wherein the molding layer further comprises a portion arranged between the solder resist patterns and the semiconductor chip. ### Claim 17 A semiconductor package comprising: a wiring board including a wiring pattern; a solder resist layer on a top surface of the wiring board, the solder resist layer defining an opening that exposes the wiring pattern; a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board; a molding layer in the opening between the wiring board and the semiconductor chip and molding the wiring board and the semiconductor chip; solder resist patterns arranged in the opening between the wiring board and the semiconductor chip and surrounded by the molding layer; and a plurality of signal bumps surrounded by the molding layer between the wiring board and the semiconductor chip, the plurality of signal bumps electrically connecting the wiring board and the semiconductor chip, wherein the plurality of signal bumps are arranged in a line under a center of the semiconductor chip along a first horizontal direction, and wherein the solder resist patterns are arranged in a line along the first horizontal direction under a first edge of the semiconductor chip extending in the first horizontal direction. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein the solder resist patterns are arranged on one side of the plurality of signal bumps, and wherein the solder resist patterns are not arranged on an other side of the plurality of signal bumps. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the semiconductor chip further comprises a second edge extending in a second horizontal direction intersecting with the first horizontal direction, and wherein the solder resist patterns further comprise a portion arranged under the second edge. ### Claim 20 (depends on 19) The semiconductor package of claim 19, wherein the solder resist patterns are arranged along a line under the second edge in the second horizontal direction.