Single ended sense amplifier with current pulse circuit
AssigneeGlobalFoundries U.S. Inc.
InventorsSiva Kumar Chinthu, Suresh Pasupula, Devesh Dwivedi, Chunsung Chiang
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Abstract
Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.
Claims20
A memory circuit, comprising:
- a bit cell having a resistor configurable to a low resistive state and a high resistive state;
- a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell;
- and
- a NAND gate having an output coupled to a gate of the PMOS transistor, wherein a first input of the NAND gate is controlled by a state of the bit cell;
- wherein a source of the PMOS transistor is connected to a current source, and wherein the current source increases an applied read current to the data path with an injected current pulse in response to detection of a low to high transition of a resistive state of the bit cell.
A sense amplifier, comprising:
- a bit cell coupled to a sensing circuit via a data path wherein the bit cell includes a resistor configurable to a low resistive state and a high resistive state;
- a transistor coupled between a current source and the data path;
- and
- a NAND gate having an output coupled to a gate of the transistor, wherein a first input of the NAND gate is controlled by an output node of the sensing circuit.
A sense amplifier, comprising:
- a bit cell coupled to a sensing circuit via a data path wherein the bit cell includes a resistor configurable to a low resistive state and a high resistive state;
- a transistor coupled between a current source and the data path;
- and
- a pulse generation circuit coupled to a gate of the transistor that causes a pulse current to be injected on the data path during low to high resistive state transitions of the bit cell.
Dependencies are inferred from the claim text.