# US 2025/0165784 A1 · Splitting of input data for processing in neural network processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0165784 A1 - Document ID: US20250165784A1 - Status: Published application - Kind: A1 - Application number: 19/030,424 - Filed: 2025-01-17 - Published: 2025-05-22 - Earliest claimed: 2018-05-04 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Christopher L. MILLS - Web page: https://patentgrep.com/patent/US20250165784A1 ## CPC - G06N 3/063: using electronic means - G06N 3/08: Learning methods - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/06: Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons - G06N 7/04: Physical realisation - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract Embodiments of the present disclosure relate to splitting input data into smaller units for loading into a data buffer and neural engines in a neural processor circuit for performing neural network operations. The input data of a large size is split into slices and each slice is again split into tiles. The tile is uploaded from an external source to a data buffer inside the neural processor circuit but outside the neural engines. Each tile is again split into work units sized for storing in an input buffer circuit inside each neural engine. The input data stored in the data buffer and the input buffer circuit is reused by the neural engines to reduce re-fetching of input data. Operations of splitting the input data are performed at various components of the neural processor circuit under the management of rasterizers provided in these components. ## Claims ### Claim 1 A processor circuit, comprising: a plurality of neural engines, each comprising an input buffer circuit; a data buffer circuit configured to provide, to a respective input buffer circuit of at least one neural engine of the plurality of neural engines, a first set of work units of input data, wherein the at least one neural engine is configured to process the set of work units based on a set of kernels; and a rasterizer circuit configured to instruct the data buffer circuit to obtain a second set of work units of the input data after processing the first set of work units by the at least one neural engine is completed. ### Claim 2 (depends on 1) The processor circuit of claim 1, wherein the rasterizer circuit is further configured to instruct the data buffer circuit to provide, to the respective input buffer circuit of the at least one neural engine, the second set of work units of the input data. ### Claim 3 (depends on 1) The processor circuit of claim 1, wherein the respective input buffer circuit of the at least one neural engine comprises another rasterizer circuit, wherein the other rasterizer circuit is configured to instruct the respective input buffer circuit to shift a portion of the first set of work units of the input data. ### Claim 4 (depends on 3) The processor circuit of claim 3, wherein the at least one neural engine comprises a multiply-accumulator circuit configured to perform a digital multiply and add operation on the shifted portion of the first set of work units of the input data. ### Claim 5 (depends on 4) The processor circuit of claim 4, wherein the multiply-accumulator circuit is further configured to generate a processed digital value based on the digital multiply and add operation on the shifted portion of the respective work unit using the set of kernels, wherein the at least one neural engine further comprises an accumulator configured to store the processed digital value. ### Claim 6 (depends on 1) The processor circuit of claim 1, further comprising a direct memory access (DMA) circuit configured to obtain the first set of work units from a memory coupled to the processor circuit and provide the first set of work units to the data buffer circuit. ### Claim 7 (depends on 1) The processor circuit of claim 1, further comprising a neural task manager circuit configured to provide task information to program the rasterizer circuit, wherein the task information indicates at least a dimension of the input data. ### Claim 8 A method, comprising: providing, by a data buffer circuit and to a respective input buffer circuit of at least one neural engine of a plurality of neural engines, a first set of work units of input data, wherein the at least one neural engine is configured to process the first set of work units based on a set of kernels; and instructing, by a rasterizer circuit, the data buffer circuit to obtain a second set of work units of the input data after processing the first set of work units by the at least one neural engine is completed. ### Claim 9 (depends on 8) The method of claim 8, further comprising instructing, by the rasterizer circuit, the data buffer circuit to provide, to the respective input buffer circuit of the at least one neural engine, the second set of work units of the input data. ### Claim 10 (depends on 8) The method of claim 8, further comprising instructing, by another rasterizer circuit, the respective input buffer circuit to shift a portion of the first set of work units of the input data, wherein the other rasterizer circuit is included in the at least one neural engine. ### Claim 11 (depends on 10) The method of claim 10, further comprising performing, by a multiply-accumulator circuit of the at least one neural engine, a digital multiply and add operation on the shifted portion of the first set of work units of the input data. ### Claim 12 (depends on 11) The method of claim 11, further comprising, by the multiply-accumulator circuit: generating a processed digital value based on the digital multiply and add operation on the shifted portion of the respective work unit using the kernel; and storing, by an accumulator of the at least one neural engine, the processed digital value. ### Claim 13 (depends on 8) The method of claim 8, further comprising: obtaining, by a direct memory access (DMA) circuit, the first set of work units from a memory; and providing, by the DMA circuit, the first set of work units to the data buffer circuit. ### Claim 14 (depends on 8) The method of claim 8, further comprising providing, by a neural task manager circuit, task information to program the rasterizer circuit, wherein the task information indicates at least a dimension of the input data. ### Claim 15 A system, comprising: a memory; and a processor circuit, comprising: at least one neural engine comprising a respective input buffer circuit; a data buffer circuit configured to provide, to the respective input buffer circuit of the at least one neural engine, a first set of work units of input data, wherein the at least one neural engine is configured to process the set of work units based on a set of kernels; and a rasterizer circuit configured to instruct the data buffer circuit to obtain a second set of work units of the input data after processing the first set of work units by the at least one neural engine is completed. ### Claim 16 (depends on 15) The system of claim 15, wherein the rasterizer circuit is further configured to instruct the data buffer circuit to provide, to the respective input buffer circuit of the at least one neural engine, the second set of work units of the input data. ### Claim 17 (depends on 15) The system of claim 15, wherein the respective input buffer circuit of the at least one neural engine comprises another rasterizer circuit, wherein the other rasterizer circuit is configured to instruct the respective input buffer circuit to shift a portion of the first set of work units of the input data. ### Claim 18 (depends on 17) The system of claim 17, wherein the at least one neural engine comprises a multiply-accumulator circuit configured to perform a digital multiply and add operation on the shifted portion of the first set of work units of the input data. ### Claim 19 (depends on 18) The system of claim 18, wherein the multiply-accumulator circuit is further configured to generate a processed digital value based on the digital multiply and add operation on the shifted portion of the respective work unit using the set of kernels, and wherein the at least one neural engine further comprises an accumulator configured to store the processed digital value. ### Claim 20 (depends on 15) The system of claim 15, further comprising a direct memory access (DMA) circuit configured to: obtain the first set of work units from the memory; and provide the first set of work units to the data buffer circuit.