# US 2025/0165769 A1 · Utilization-based mapping for three dimensional analog in-memory computing

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- Number: US 2025/0165769 A1
- Document ID: US20250165769A1
- Status: Published application
- Kind: A1
- Application number: 18/513,491
- Filed: 2023-11-17
- Published: 2025-05-22
- Earliest claimed: 2023-11-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Athanasios Vasilopoulos; Julian Röttger Büchel; Manuel Le Gallo-Bourdeau; Irem Boybat Kara; Abbas Rahimi; Abu Sebastian
- Web page: https://patentgrep.com/patent/US20250165769A1

## CPC

- G06N 3/08: Learning methods
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- G06N 5/04: Inference or reasoning models
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A method for balancing utilization of tiles in an analog in-memory computing system includes identifying, by a computer processor, a plurality of tiles in the analog in-memory computing system. The computer processor receives a plurality of layers in a neural network being processed by the analog in-memory computing system. The computer processor maps the plurality of layers in the neural network to the plurality of tiles. The computer processor determines a number of operations for each of the tiles in the plurality of tiles. The computer processor determines an equalized utilization rate for the tiles in the plurality of tiles. In addition, the computer processor assigns the layers to the plurality of tiles. The tiles are assigned so that a first utilization rate of a first tile is balanced relative to a second utilization rate of a second tile in the analog in-memory computing system.

## Claims

### Claim 1

A computer program product for balancing utilization of tiles in an analog in-memory computing system, the computer program product comprising:
one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising:
identifying, by a computer processor, a plurality of tiles in the analog in-memory computing system;
receiving, by the computer processor, a plurality of layers in a neural network being processed by the analog in-memory computing system;
defining, by the computer processor, a number of operations for each layer in the plurality of layers;
assigning a utilization rate to each layer;
determining, by the computer processor, a target equalized utilization rate based on the identified plurality of tiles; and
assigning the layers to the plurality of tiles, by the computer processor, wherein a first utilization rate of a first tile is balanced relative to a second utilization rate of a second tile in the analog in-memory computing system.

### Claim 2 (depends on 1)

The computer program product of claim 1, wherein:
the program instructions further comprise receiving, by the computer processor, a locality constraint; and
assigning the layers to the plurality of tiles is based at least in part on the locality constraint.

### Claim 3 (depends on 2)

The computer program product of claim 2, wherein the locality constraint includes using only successive layers in the tiles.

### Claim 4 (depends on 2)

The computer program product of claim 2, wherein the program instructions further comprise selecting the locality constraint based on reducing latency in an output of the neural network.

### Claim 5 (depends on 1)

The computer program product of claim 1, wherein:
the neural network operates under one or more architecture-specific restraints; and
the determination of the equalized utilization rate for the tiles is made under the one or more architecture-specific restraints.

### Claim 6 (depends on 1)

The computer program product of claim 1, wherein the analog in-memory computing system comprises a plurality of neural network models, and wherein the program instructions further comprise:
receiving an input token of an image for processing by the plurality of neural network models;
mapping the plurality of neural network models to a planar space;
dividing the planar space into a plurality of subspaces; and
assigning the plurality of neural network models to the subspaces, wherein an activation rate for the processing of the input token is evenly distributed amongst the subspaces.

### Claim 7 (depends on 1)

The computer program product of claim 1, wherein:
the analog in-memory computing system comprises a first neural network model and a second neural network model; and
the program instructions further comprise:
stacking layers of a first tile from the first neural network model with layers of the first tile from the second neural network model into a new tile; and
determining the target equalized utilization rate for the new tile.

### Claim 8

A computer implemented method for balancing utilization of tiles in an analog in-memory computing system, comprising:
identifying, by a computer processor, a plurality of tiles in the analog in-memory computing system;
receiving, by the computer processor, a plurality of layers in a neural network being processed by the analog in-memory computing system;
defining, by the computer processor, a number of operations for each layer in the plurality of layers;
assigning a utilization rate to each layer;
determining, by the computer processor, a target equalized utilization rate based on the identified plurality of tiles; and
assigning the layers to the plurality of tiles, by the computer processor, wherein a first utilization rate of a first tile is balanced relative to a second utilization rate of a second tile in the analog in-memory computing system.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
receiving, by the computer processor, a locality constraint; and
wherein assigning the layers to the plurality of tiles is based at least in part on the locality constraint.

### Claim 10 (depends on 9)

The method of claim 9, wherein the locality constraint includes using only successive layers in the tiles.

### Claim 11 (depends on 9)

The method of claim 9, further comprising selecting the locality constraint based on reducing latency in an output of the neural network.

### Claim 12 (depends on 8)

The method of claim 8, wherein:
the neural network operates under one or more architecture-specific restraints; and
the determination of the equalized utilization rate for the tiles is made under the one or more architecture-specific restraints.

### Claim 13 (depends on 8)

The method of claim 8, wherein the analog in-memory computing system comprises a plurality of neural network models, and wherein the method further comprises:
receiving an input token of an image for processing by the plurality of neural network models;
mapping the plurality of neural network models to a planar space;
dividing the planar space into a plurality of subspaces; and
assigning the plurality of neural network models to the subspaces, wherein an activation rate for the processing of the input token is evenly distributed amongst the subspaces.

### Claim 14 (depends on 8)

The method of claim 8, wherein:
the analog in-memory computing system comprises a first neural network model and a second neural network model; and
the method further comprises:
stacking layers of a first tile from the first neural network model with layers of the first tile from the second neural network model into a new tile; and
determining the target equalized utilization rate for the new tile.

### Claim 15

A computing device configured to balance utilization of tiles in an analog in-memory computing system, comprising:
a processor operating an analog in-memory computing engine in the analog in-memory computing system; and
a memory coupled to the processor, the memory storing instructions to cause the processor to perform acts comprising:
identifying, by a computer processor, a plurality of tiles in the analog in-memory computing system;
receiving, by the computer processor, a plurality of layers in a neural network being processed by the analog in-memory computing system;
defining, by the computer processor, a number of operations for each layer in the plurality of layers;
assigning a utilization rate to each layer;
determining, by the computer processor, a target equalized utilization rate based on the identified plurality of tiles; and
assigning the layers to the plurality of tiles, by the computer processor, wherein a first utilization rate of a first tile is balanced relative to a second utilization rate of a second tile in the analog in-memory computing system.

### Claim 16 (depends on 15)

The computing device of claim 15, wherein the instructions cause the processor to perform further acts comprising:
receiving, by the computer processor, a locality constraint; and
wherein assigning the layers to the plurality of tiles is based at least in part on the locality constraint.

### Claim 17 (depends on 16)

The computing device of claim 16, wherein the instructions cause the processor to perform further acts comprising selecting the locality constraint based on reducing latency in an output of the neural network.

### Claim 18 (depends on 15)

The computing device of claim 15, wherein:
the neural network operates under one or more architecture-specific restraints; and
the determination of the equalized utilization rate for the tiles is made under the one or more architecture-specific restraints.

### Claim 19 (depends on 15)

The computing device of claim 15, wherein the analog in-memory computing system comprises a plurality of neural network models, and wherein the memory storing instructions cause the processor to perform acts further comprising:
receiving an input token of an image for processing by the plurality of neural network models;
mapping the plurality of neural network models to a planar space;
dividing the planar space into a plurality of subspaces; and
assigning the plurality of neural network models to the subspaces, wherein an activation rate for the processing of the input token is evenly distributed amongst the subspaces.

### Claim 20 (depends on 15)

The computing device of claim 15, wherein:
the analog in-memory computing system comprises a first neural network model and a second neural network model; and
the instructions cause the processor to perform further acts comprising:
stacking layers of a first tile from the first neural network model with layers of the first tile from the second neural network model into a new tile; and
determining the target equalized utilization rate for the new tile.