# US 2025/0165403 A1 · Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2025/0165403 A1 - Document ID: US20250165403A1 - Status: Published application - Kind: A1 - Application number: 19/024,060 - Filed: 2025-01-16 - Published: 2025-05-22 - Earliest claimed: 2019-06-28 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sanjay Subbarao; James Fitzpatrick - Web page: https://patentgrep.com/patent/US20250165403A1 ## CPC - G06F 12/0882: Page mode - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0811: with multilevel cache hierarchies - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions. ## Claims ### Claim 1 A device, comprising: an interface configured to communicate with a host system; a plurality of media units; and a logic circuit configured to manage programming of pages in the media units to accommodate a predetermined characteristics of data. ### Claim 2 (depends on 1) The device of claim 1, wherein the predetermined characteristics is associated with a rate of data transfer between the device and host system over the interface. ### Claim 3 (depends on 2) The device of claim 2, wherein the logic circuit is configured to manage the programming of the pages in the media units to accommodate the rate to be constant. ### Claim 4 (depends on 3) The device of claim 3, wherein the logic circuit is configured to perform multi-pass programming of pages in the media units. ### Claim 5 (depends on 4) The device of claim 4, wherein the multi-pass programming includes a plurality of atomic programming operations; and the logic circuit is configured to manage transitions between modes of programming a memory cell in the atomic programming operations. ### Claim 6 (depends on 4) The device of claim 4, wherein the multi-pass programming includes: a first atomic programming of a single data page of a predetermined size in the media units; and a second atomic programming of two data pages each having the predetermined size in the media units. ### Claim 7 (depends on 6) The device of claim 6, wherein the logic circuit is configured to determine a count of first transitions in modes of programming a memory cell in the first atomic programming and manage, based on the count, second transitions in modes of programming a memory cell in the second atomic programming. ### Claim 8 (depends on 7) The device of claim 7, wherein the first transitions are transitions from a first mode to a second mode; and the first mode and the second mode are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell. ### Claim 9 A method, comprising: communicating, by a device having a plurality of media units, with a host system to write data from the host system into the media units; and managing, by the device, programming of pages in the media units to accommodate a predetermined characteristics of data. ### Claim 10 (depends on 9) The method of claim 9, wherein the predetermined characteristics is associated with a rate of data transfer between the device and host system. ### Claim 11 (depends on 10) The method of claim 10, further comprising: accommodating, based on the managing, the rate to be constant. ### Claim 12 (depends on 11) The method of claim 11, wherein the programming of the pages in the media units includes multi-pass programming of the pages in the media units. ### Claim 13 (depends on 12) The method of claim 12, wherein the multi-pass programming includes a plurality of atomic programming operations; and the managing includes managing transitions between modes of programming a memory cell in the atomic programming operations. ### Claim 14 (depends on 13) The method of claim 13, wherein the multi-pass programming includes: a first atomic programming of a single data page of a predetermined size in the media units; and a second atomic programming of two data pages each having the predetermined size in the media units. ### Claim 15 (depends on 14) The method of claim 14, wherein the managing of the transitions includes: determining a count of first transitions in modes of programming a memory cell in the first atomic programming; and managing, based on the count, second transitions in modes of programming a memory cell in the second atomic programming. ### Claim 16 (depends on 15) The method of claim 15, wherein the first transitions are transitions from a first mode to a second mode; and the first mode and the second mode are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell. ### Claim 17 A computing system, comprising: a device having a plurality of media units; and a host system connected to the device to write data into the device; wherein the device is configured to manage programming of pages in the media units to accommodate a constant rate of data transfer. ### Claim 18 (depends on 17) The computing system of claim 17, wherein the device configured to perform multi-pass programming of pages in the media units via a plurality of atomic programming operations, including a first atomic programming of a single data page of a predetermined size in the media units and a second atomic programming of two data pages each having the predetermined size in the media units; and wherein the device is further configured to manage transitions between modes of programming a memory cell in the atomic programming operations. ### Claim 19 (depends on 18) The computing system of claim 18, wherein the device is configured to determine a count of first transitions in modes of programming a memory cell in the first atomic programming and manage, based on the count, second transitions in modes of programming a memory cell in the second atomic programming. ### Claim 20 (depends on 19) The computing system of claim 19, wherein the first transitions are transitions from a first mode to a second mode; and the first mode and the second mode are different ones of: no programming; programming to store one bit in each memory cell; programming to store two bits in each memory cell; programming to store three bits in each memory cell; and programming to store four bits in each memory cell.